From 6d08c1800c7d313c3e6be9fe2c7124df02749665 Mon Sep 17 00:00:00 2001 From: zwelch Date: Thu, 2 Jul 2009 04:55:35 +0000 Subject: David Brownell : Prepare the DaVinci PLL code to support the version 0x0E module used in newer chips (e.g. dm365): rename the original code so it's specific to version 0x02 PLL modules, and update the dm355evm code to use that new name. Fix two minor bugs in that version 2 code: sysclk3 setup used the sysclk2 divider address (affecting video processing on dm355, no worry for now) and sysclk2 setup had a syntax error. Also minor fixups to dm355evm, mostly to permit use of RTCK. git-svn-id: svn://svn.berlios.de/openocd/trunk@2447 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- tcl/board/dm355evm.cfg | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'tcl/board') diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 9e6dc73b..9b32ef9e 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -1,4 +1,3 @@ -# # DM355 EVM board # http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html # http://c6000.spectrumdigital.com/evmdm355/ @@ -22,7 +21,7 @@ proc dm355evm_init {} { puts "Initialize DM355 EVM board" # CLKIN = 24 MHz ... can't talk quickly to ARM yet - jtag_khz 1500 + jtag_rclk 1500 ######################## # PLL1 = 432 MHz (/8, x144) @@ -37,10 +36,10 @@ proc dm355evm_init {} { set pll_divs [dict create] dict set pll_divs div3 16 dict set pll_divs div4 8 - pll_setup $addr 144 $pll_divs + pll_v02_setup $addr 144 $pll_divs # ARM is now running at 216 MHz, so JTAG can go faster - jtag_khz 20000 + jtag_rclk 20000 ######################## # PLL2 = 342 MHz (/8, x114) @@ -50,7 +49,7 @@ proc dm355evm_init {} { set addr [dict get $dm355 pllc2] set pll_divs [dict create] dict set pll_divs prediv 8 - pll_setup $addr 114 $pll_divs + pll_v02_setup $addr 114 $pll_divs ######################## # PINMUX -- cgit v1.2.3