From dbbc9c41f7db210b0a4e226540a28e0a8a5019bf Mon Sep 17 00:00:00 2001
From: zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 27 May 2009 06:49:24 +0000
Subject: Move TCL script files -- Step 2 of 2: - Move src/tcl to tcl/. -
 Update top Makefile.am to use new path name.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1919 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 tcl/chip/atmel/at91/rtt.tcl | 56 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 tcl/chip/atmel/at91/rtt.tcl

(limited to 'tcl/chip/atmel/at91/rtt.tcl')

diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl
new file mode 100644
index 00000000..9c60300e
--- /dev/null
+++ b/tcl/chip/atmel/at91/rtt.tcl
@@ -0,0 +1,56 @@
+
+set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
+set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
+set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
+set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
+global RTTC_RTMR
+global RTTC_RTAR
+global RTTC_RTVR
+global RTTC_RTSR
+
+proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
+    set rtpres [expr $VAL & 0x0ffff]
+    global BIT16 BIT17
+    if { $rtpres == 0 } {
+	set rtpres 65536;
+    } 
+    global AT91C_SLOWOSC_FREQ
+    # Nasty hack, make this a float by tacking a .0 on the end
+    # otherwise, jim makes the value an integer
+    set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
+    puts [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
+    if { $VAL & $BIT16 } {
+	puts "\tBit16 -> Alarm IRQ Enabled"
+    } else {
+	puts "\tBit16 -> Alarm IRQ Disabled"
+    }
+    if { $VAL & $BIT17 } {
+	puts "\tBit17 -> RTC Inc IRQ Enabled"
+    } else {
+	puts "\tBit17 -> RTC Inc IRQ Disabled"
+    }
+    # Bit 18 is write only.
+}
+
+proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
+    global BIT0 BIT1
+    if { $VAL & $BIT0 } {
+	puts "\tBit0 -> ALARM PENDING"
+    } else {
+	puts "\tBit0 -> alarm not pending"
+    }
+    if { $VAL & $BIT1 } {
+	puts "\tBit0 -> RTINC PENDING"
+    } else {
+	puts "\tBit0 -> rtinc not pending"
+    }
+}
+
+proc show_RTTC { } {
+    
+    show_mmr32_reg RTTC_RTMR
+    show_mmr32_reg RTTC_RTAR
+    show_mmr32_reg RTTC_RTVR
+    show_mmr32_reg RTTC_RTSR
+}
+
-- 
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