From 108028112fdf285cd74eaf50d6a353a09039bb7f Mon Sep 17 00:00:00 2001 From: dbrownell Date: Mon, 21 Sep 2009 00:37:58 +0000 Subject: Ensure that DaVinci chips can't start with a too-fast JTAG clock. It can be sped up later, once it's known the PLLs are active. Note that modern tools from TI all use adaptive clocking; and that if that's done with OpenOCD, "too fast" is also a non-issue. git-svn-id: svn://svn.berlios.de/openocd/trunk@2740 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- tcl/target/ti_dm365.cfg | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tcl/target/ti_dm365.cfg') diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index 4f22ea27..06a52d28 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -88,6 +88,12 @@ $_TARGETNAME configure \ -work-area-size 0x4000 \ -work-area-backup 0 +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +jtag_rclk 1500 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 } + arm7_9 fast_memory_access enable arm7_9 dcc_downloads enable -- cgit v1.2.3