From 4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136 Mon Sep 17 00:00:00 2001
From: Thomas Koeller <thomas.koeller@baslerweb.com>
Date: Tue, 10 Aug 2010 14:56:43 +0200
Subject: DM36x: Disable unused SYSCLKs

Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
---
 tcl/target/davinci.cfg | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

(limited to 'tcl/target')

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index b736c6ef..11ae093f 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -197,63 +197,82 @@ proc pll_v03_setup {pll_addr mult config} {
 	# 11 - optional:  set plldiv1, plldiv2, ...
 	# NOTE:  this assumes some registers have their just-reset values:
 	#	- PLLSTAT.GOSTAT is clear when we enter
-	#	- ALNCTL has everything set
 	set aln 0
 	if { [dict exists $config div1] } {
 		set div [dict get $config div1]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0118] $div
 		set aln [expr $aln | 0x1]
+	} else {
+		mww [expr $pll_addr + 0x0118] 0
 	}
 	if { [dict exists $config div2] } {
 		set div [dict get $config div2]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x011c] $div
 		set aln [expr $aln | 0x2]
+	} else {
+		mww [expr $pll_addr + 0x011c] 0
 	}
 	if { [dict exists $config div3] } {
 		set div [dict get $config div3]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0120] $div
 		set aln [expr $aln | 0x4]
+	} else {
+		mww [expr $pll_addr + 0x0120] 0
 	}
 	if { [dict exists $config div4] } {
 		set div [dict get $config div4]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0160] $div
 		set aln [expr $aln | 0x8]
+	} else {
+		mww [expr $pll_addr + 0x0160] 0
 	}
 	if { [dict exists $config div5] } {
 		set div [dict get $config div5]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0164] $div
 		set aln [expr $aln | 0x10]
+	} else {
+		mww [expr $pll_addr + 0x0164] 0
 	}
 	if { [dict exists $config div6] } {
 		set div [dict get $config div6]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0168] $div
 		set aln [expr $aln | 0x20]
+	} else {
+		mww [expr $pll_addr + 0x0168] 0
 	}
 	if { [dict exists $config div7] } {
 		set div [dict get $config div7]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x016c] $div
 		set aln [expr $aln | 0x40]
+	} else {
+		mww [expr $pll_addr + 0x016c] 0
 	}
 	if { [dict exists $config div8] } {
 		set div [dict get $config div8]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0170] $div
 		set aln [expr $aln | 0x80]
+	} else {
+		mww [expr $pll_addr + 0x0170] 0
 	}
 	if { [dict exists $config div9] } {
 		set div [dict get $config div9]
 		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0174] $div
 		set aln [expr $aln | 0x100]
+	} else {
+		mww [expr $pll_addr + 0x0174] 0
 	}
 	if {$aln != 0} {
+		# clear pllcmd.GO
+		mww [expr $pll_addr + 0x0138] 0x00
 		# write alingment flags
 		mww [expr $pll_addr + 0x0140] $aln
 		# write pllcmd.GO; poll pllstat.GO
-- 
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