From 2dcf57363a5c1c55940e5701e5ec047c37c54560 Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Wed, 22 Feb 2012 00:06:18 +0100
Subject: A working version for my EFM board.

---
 tcl/board/olimex_efm32g880f128.cfg          |  6 +++
 tcl/chip/energymicro/efm32.tcl              |  3 ++
 tcl/interface/olimex-arm-usb-tiny-h+swd.cfg | 31 ++++++++++++
 tcl/target/efm32.cfg                        | 77 +++++++++++++++++++++++++++++
 4 files changed, 117 insertions(+)
 create mode 100644 tcl/board/olimex_efm32g880f128.cfg
 create mode 100644 tcl/chip/energymicro/efm32.tcl
 create mode 100644 tcl/interface/olimex-arm-usb-tiny-h+swd.cfg
 create mode 100644 tcl/target/efm32.cfg

(limited to 'tcl')

diff --git a/tcl/board/olimex_efm32g880f128.cfg b/tcl/board/olimex_efm32g880f128.cfg
new file mode 100644
index 00000000..ffa26d59
--- /dev/null
+++ b/tcl/board/olimex_efm32g880f128.cfg
@@ -0,0 +1,6 @@
+# # Work-area size (RAM size) = 20kB for STM32F103RB device
+# set WORKAREASIZE 0x5000
+
+# CPUIDTAP 0x2BA01477
+
+source [find target/efm32.cfg]
diff --git a/tcl/chip/energymicro/efm32.tcl b/tcl/chip/energymicro/efm32.tcl
new file mode 100644
index 00000000..1dc9bd7f
--- /dev/null
+++ b/tcl/chip/energymicro/efm32.tcl
@@ -0,0 +1,3 @@
+source [find cpu/arm/cortex_m3.tcl]
+
+# 0x2BA01477
diff --git a/tcl/interface/olimex-arm-usb-tiny-h+swd.cfg b/tcl/interface/olimex-arm-usb-tiny-h+swd.cfg
new file mode 100644
index 00000000..3c4eb990
--- /dev/null
+++ b/tcl/interface/olimex-arm-usb-tiny-h+swd.cfg
@@ -0,0 +1,31 @@
+#
+# Olimex ARM-USB-TINY-H with ARM-JTAG-SWD adapter.
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+# http://www.olimex.com/dev/arm-jtag-swd.html
+#
+
+interface ft2232_swd
+# ALl other examples have "Olimex OpenOCD JTAG ARM-USB-TINY-H", but my
+# adaptor doesn't.
+# ft2232_device_desc "Olimed Ltd."
+
+#ft2232_layout olimex-jtag
+ft2232_layout olimex-swd
+
+ft2232_vid_pid 0x15ba 0x002a
+
+# TRST is used as RnW
+# interface_signal add RnW 0x0100
+
+# TMS is used as RnW
+interface_signal add RnW 0x0008
+
+# TRST + TMS is used as RnW
+# interface_signal add RnW 0x0108
+
+interface_signal add LED 0x0800
+
+# interface_signal add SRST 0x0a00
+
+adapter_khz 10
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
new file mode 100644
index 00000000..de5384cb
--- /dev/null
+++ b/tcl/target/efm32.cfg
@@ -0,0 +1,77 @@
+# script for Energy Micro's efm32
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME efm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+# jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+# jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swd newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  set _BSTAPID4 0x06420041
+  # High density devices, Rev A
+  set _BSTAPID5 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID6 0x06418041
+  # XL line devices, Rev A
+  set _BSTAPID7 0x06430041
+}
+# jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+swd newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
+	-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
-- 
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