From c202ba7d34bd7feba88d7c0ee1aa9ef7be18bca9 Mon Sep 17 00:00:00 2001
From: Øyvind Harboe <oyvind.harboe@zylin.com>
Date: Mon, 26 Oct 2009 14:39:32 +0100
Subject: ARM11: remove old mrc/mcr commands
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Switch to new commands in config scripts

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 tcl/board/csb732.cfg      | 6 +++---
 tcl/target/c100helper.tcl | 8 ++++----
 tcl/target/imx.cfg        | 2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'tcl')

diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 17873230..9022fafc 100644
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
 	# We assume the interpreter latency is enough.
 
 	# Allow access to all coprocessors
-	arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
+	mcr 15 0 15 1 0 0x2001
 
 	# Disable MMU, caches, write buffer
-	arm11 mcr imx35.cpu 15 0 1 0 0 0x78
+	mcr 15 0 1 0 0 0x78
 
 	# Grant manager access to all domains
-	arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
+	mcr 15 0 3 0 0 0xFFFFFFFF
 
 	# Set ARM clock to 532 MHz, AHB to 133 MHz
 	mww 0x53F80004 0x1000
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index b5e01646..54fe07f0 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -436,22 +436,22 @@ proc initC100 {} {
     #	 */
     #	mov	r0, #0
     #	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-    arm11 mcr c100.cpu 15 0 7 7 0 0x0
+    mcr 15 0 7 7 0 0x0
     #	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-    arm11 mcr c100.cpu 15 0 8 7 0 0x0
+    mcr 15 0 8 7 0 0x0
 
     #	/*
     #	 * disable MMU stuff and caches
     #	 */
     #	mrc	p15, 0, r0, c1, c0, 0
-    arm11 mrc c100.cpu 15 0 1 0 0
+    mrc 15 0 1 0 0
     #	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
     #	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
     #	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
     #	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
     #	orr	r0, r0, #0x00400000	@ set bit 22 (U)
     #	mcr	p15, 0, r0, c1, c0, 0
-    arm11 mcr c100.cpu 15 0 1 0 0 0x401002
+    mcr 15 0 1 0 0 0x401002
     # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
     # APB init
     #    	// Setting APB Bus Wait states to 1, set post write
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index 16773fa5..bfcc6525 100644
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -10,7 +10,7 @@ proc setc15 {regs value} {
 
 	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
 
-	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+	mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
 }
 
 
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