From 4b06fa39ae2a96af73b7f2e6907396df198b083f Mon Sep 17 00:00:00 2001 From: mifi Date: Sat, 1 Mar 2008 15:41:14 +0000 Subject: - added sam7s256 test example, and test result git-svn-id: svn://svn.berlios.de/openocd/trunk@415 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- testing/examples/SAM7S256Test/prj/sam7s256_reset.script | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 testing/examples/SAM7S256Test/prj/sam7s256_reset.script (limited to 'testing/examples/SAM7S256Test/prj/sam7s256_reset.script') diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_reset.script b/testing/examples/SAM7S256Test/prj/sam7s256_reset.script new file mode 100644 index 00000000..ff609b01 --- /dev/null +++ b/testing/examples/SAM7S256Test/prj/sam7s256_reset.script @@ -0,0 +1,17 @@ +# +# Init - taken form the script openocd_at91sam7_ecr.script +# +# I take this script from the following page: +# +# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html +# +mww 0xfffffd44 0x00008000 # disable watchdog +mww 0xfffffd08 0xa5000001 # enable user reset +mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +sleep 10 +mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz +sleep 10 +mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz +sleep 10 +mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +sleep 100 -- cgit v1.2.3