/***************************************************************************
 *   Copyright (C) 2005, 2007 by Dominic Rath                              *
 *   Dominic.Rath@gmx.de                                                   *
 *   Copyright (C) 2009 Michael Schwingen                                  *
 *   michael@schwingen.org                                                 *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "replacements.h"

#include "cfi.h"
#include "non_cfi.h"

#include "flash.h"
#include "target.h"
#include "log.h"
#include "armv4_5.h"
#include "algorithm.h"
#include "binarybuffer.h"
#include "types.h"

#include <stdlib.h>
#include <string.h>
#include <unistd.h>

static int cfi_register_commands(struct command_context_s *cmd_ctx);
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int cfi_erase(struct flash_bank_s *bank, int first, int last);
static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
static int cfi_probe(struct flash_bank_s *bank);
static int cfi_auto_probe(struct flash_bank_s *bank);
static int cfi_protect_check(struct flash_bank_s *bank);
static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);

//static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);

#define CFI_MAX_BUS_WIDTH	4
#define CFI_MAX_CHIP_WIDTH	4

/* defines internal maximum size for code fragment in cfi_intel_write_block() */
#define CFI_MAX_INTEL_CODESIZE 256

flash_driver_t cfi_flash =
{
	.name = "cfi",
	.register_commands = cfi_register_commands,
	.flash_bank_command = cfi_flash_bank_command,
	.erase = cfi_erase,
	.protect = cfi_protect,
	.write = cfi_write,
	.probe = cfi_probe,
	.auto_probe = cfi_auto_probe,
	.erase_check = default_flash_blank_check,
	.protect_check = cfi_protect_check,
	.info = cfi_info
};

static cfi_unlock_addresses_t cfi_unlock_addresses[] =
{
	[CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
	[CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
};

/* CFI fixups foward declarations */
static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);

/* fixup after reading cmdset 0002 primary query table */
static cfi_fixup_t cfi_0002_fixups[] = {
	{CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
	{CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
	{CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
	{CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
	{CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
	{CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
	{0, 0, NULL, NULL}
};

/* fixup after reading cmdset 0001 primary query table */
static cfi_fixup_t cfi_0001_fixups[] = {
	{0, 0, NULL, NULL}
};

static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_fixup_t *f;

	for (f = fixups; f->fixup; f++)
	{
		if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
			((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
		{
			f->fixup(bank, f->param);
		}
	}
}

/* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
__inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
{
	/* while the sector list isn't built, only accesses to sector 0 work */
	if (sector == 0)
		return bank->base + offset * bank->bus_width;
	else
	{
		if (!bank->sectors)
		{
			LOG_ERROR("BUG: sector list not yet built");
			exit(-1);
		}
		return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
	}

}

static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
{
	int i;

	/* clear whole buffer, to ensure bits that exceed the bus_width
	 * are set to zero
	 */
	for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
		cmd_buf[i] = 0;

	if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
	{
		for (i = bank->bus_width; i > 0; i--)
		{
			*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
		}
	}
	else
	{
		for (i = 1; i <= bank->bus_width; i++)
		{
			*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
		}
	}
}

/* read unsigned 8-bit value from the bank
 * flash banks are expected to be made of similar chips
 * the query result should be the same for all
 */
static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
{
	target_t *target = bank->target;
	u8 data[CFI_MAX_BUS_WIDTH];

	target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);

	if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
		return data[0];
	else
		return data[bank->bus_width - 1];
}

/* read unsigned 8-bit value from the bank
 * in case of a bank made of multiple chips,
 * the individual values are ORed
 */
static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
{
	target_t *target = bank->target;
	u8 data[CFI_MAX_BUS_WIDTH];
	int i;

	target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);

	if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
	{
		for (i = 0; i < bank->bus_width / bank->chip_width; i++)
			data[0] |= data[i];

		return data[0];
	}
	else
	{
		u8 value = 0;
		for (i = 0; i < bank->bus_width / bank->chip_width; i++)
			value |= data[bank->bus_width - 1 - i];

		return value;
	}
}

static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
{
	target_t *target = bank->target;
	u8 data[CFI_MAX_BUS_WIDTH * 2];

	target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);

	if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
		return data[0] | data[bank->bus_width] << 8;
	else
		return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
}

static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
{
	target_t *target = bank->target;
	u8 data[CFI_MAX_BUS_WIDTH * 4];

	target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);

	if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
		return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
	else
		return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
				data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
}

static void cfi_intel_clear_status_register(flash_bank_t *bank)
{
	target_t *target = bank->target;
	u8 command[8];

	if (target->state != TARGET_HALTED)
	{
		LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
		exit(-1);
	}

	cfi_command(bank, 0x50, command);
	target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}

u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
{
	u8 status;

	while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
	{
		LOG_DEBUG("status: 0x%x", status);
		alive_sleep(1);
	}

	/* mask out bit 0 (reserved) */
	status = status & 0xfe;

	LOG_DEBUG("status: 0x%x", status);

	if ((status & 0x80) != 0x80)
	{
		LOG_ERROR("timeout while waiting for WSM to become ready");
	}
	else if (status != 0x80)
	{
		LOG_ERROR("status register: 0x%x", status);
		if (status & 0x2)
			LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
		if (status & 0x4)
			LOG_ERROR("Program suspended");
		if (status & 0x8)
			LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
		if (status & 0x10)
			LOG_ERROR("Program Error / Error in Setting Lock-Bit");
		if (status & 0x20)
			LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
		if (status & 0x40)
			LOG_ERROR("Block Erase Suspended");

		cfi_intel_clear_status_register(bank);
	}

	return status;
}

int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
{
	u8 status, oldstatus;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	oldstatus = cfi_get_u8(bank, 0, 0x0);

	do {
		status = cfi_get_u8(bank, 0, 0x0);
		if ((status ^ oldstatus) & 0x40) {
			if (status & cfi_info->status_poll_mask & 0x20) {
				oldstatus = cfi_get_u8(bank, 0, 0x0);
				status = cfi_get_u8(bank, 0, 0x0);
				if ((status ^ oldstatus) & 0x40) {
					LOG_ERROR("dq5 timeout, status: 0x%x", status);
					return(ERROR_FLASH_OPERATION_FAILED);
				} else {
					LOG_DEBUG("status: 0x%x", status);
					return(ERROR_OK);
				}
			}
		} else { /* no toggle: finished, OK */
			LOG_DEBUG("status: 0x%x", status);
			return(ERROR_OK);
		}

		oldstatus = status;
		alive_sleep(1);
	} while (timeout-- > 0);

	LOG_ERROR("timeout, status: 0x%x", status);

	return(ERROR_FLASH_BUSY);
}

static int cfi_read_intel_pri_ext(flash_bank_t *bank)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
	target_t *target = bank->target;
	u8 command[8];

	cfi_info->pri_ext = pri_ext;

	pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
	pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
	pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);

	if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
	{
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		cfi_command(bank, 0xff, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		LOG_ERROR("Could not read bank flash bank information");
		return ERROR_FLASH_BANK_INVALID;
	}

	pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
	pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);

	pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
	pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
	pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);

	LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);

	pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
	pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);

	LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
		  (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
		  (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);

	pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
	if (pri_ext->num_protection_fields != 1)
	{
		LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
	}

	pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
	pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
	pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);

	LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);

	return ERROR_OK;
}

static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
	target_t *target = bank->target;
	u8 command[8];

	cfi_info->pri_ext = pri_ext;

	pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
	pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
	pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);

	if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
	{
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		LOG_ERROR("Could not read spansion bank information");
		return ERROR_FLASH_BANK_INVALID;
	}

	pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
	pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);

	pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
	pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
	pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
	pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
	pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
	pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
	pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
	pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
	pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
	pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
	pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);

	LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
	      pri_ext->EraseSuspend, pri_ext->BlkProt);

	LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
	      pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);

	LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);


	LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
		  (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
		  (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);

	LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);

	/* default values for implementation specific workarounds */
	pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
	pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
	pri_ext->_reversed_geometry = 0;

	return ERROR_OK;
}

static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
{
	int retval;
	cfi_atmel_pri_ext_t atmel_pri_ext;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
	target_t *target = bank->target;
	u8 command[8];

	/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
	 * but a different primary extended query table.
	 * We read the atmel table, and prepare a valid AMD/Spansion query table.
	 */

	memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));

	cfi_info->pri_ext = pri_ext;

	atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
	atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
	atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);

	if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
	{
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		LOG_ERROR("Could not read atmel bank information");
		return ERROR_FLASH_BANK_INVALID;
	}

	pri_ext->pri[0] = atmel_pri_ext.pri[0];
	pri_ext->pri[1] = atmel_pri_ext.pri[1];
	pri_ext->pri[2] = atmel_pri_ext.pri[2];

	atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
	atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);

	LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);

	pri_ext->major_version = atmel_pri_ext.major_version;
	pri_ext->minor_version = atmel_pri_ext.minor_version;

	atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
	atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
	atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
	atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);

	LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
		atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);

	if (atmel_pri_ext.features & 0x02)
		pri_ext->EraseSuspend = 2;

	if (atmel_pri_ext.bottom_boot)
		pri_ext->TopBottom = 2;
	else
		pri_ext->TopBottom = 3;

	pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
	pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;

	return ERROR_OK;
}

static int cfi_read_0002_pri_ext(flash_bank_t *bank)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	if (cfi_info->manufacturer == CFI_MFR_ATMEL)
	{
		return cfi_read_atmel_pri_ext(bank);
	}
	else
	{
		return cfi_read_spansion_pri_ext(bank);
	}
}

static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
	int printed;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;

	printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
			   pri_ext->pri[1], pri_ext->pri[2],
			   pri_ext->major_version, pri_ext->minor_version);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
			   (pri_ext->SiliconRevision) >> 2,
			   (pri_ext->SiliconRevision) & 0x03);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
			   pri_ext->EraseSuspend,
			   pri_ext->BlkProt);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
		(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
		(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);

	return ERROR_OK;
}

static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
	int printed;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;

	printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
		(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
		(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);

	return ERROR_OK;
}

static int cfi_register_commands(struct command_context_s *cmd_ctx)
{
	/*command_t *cfi_cmd = */
	register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
	/*
	register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
					 "print part id of cfi flash bank <num>");
	*/
	return ERROR_OK;
}

/* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 */
static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
	cfi_flash_bank_t *cfi_info;
	int i;
	(void) cmd_ctx;
	(void) cmd;

	if (argc < 6)
	{
		LOG_WARNING("incomplete flash_bank cfi configuration");
		return ERROR_FLASH_BANK_INVALID;
	}

	if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
		|| (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
	{
		LOG_ERROR("chip and bus width have to specified in bytes");
		return ERROR_FLASH_BANK_INVALID;
	}

	cfi_info = malloc(sizeof(cfi_flash_bank_t));
	cfi_info->probed = 0;
	bank->driver_priv = cfi_info;

	cfi_info->write_algorithm = NULL;

	cfi_info->x16_as_x8 = 0;
	cfi_info->jedec_probe = 0;
	cfi_info->not_cfi = 0;

	for (i = 6; i < argc; i++)
	{
		if (strcmp(args[i], "x16_as_x8") == 0)
		{
			cfi_info->x16_as_x8 = 1;
		}
		else if (strcmp(args[i], "jedec_probe") == 0)
		{
			cfi_info->jedec_probe = 1;
		}
	}

	cfi_info->write_algorithm = NULL;

	/* bank wasn't probed yet */
	cfi_info->qry[0] = -1;

	return ERROR_OK;
}

static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u8 command[8];
	int i;

	cfi_intel_clear_status_register(bank);

	for (i = first; i <= last; i++)
	{
		cfi_command(bank, 0x20, command);
		if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0xd0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
			bank->sectors[i].is_erased = 1;
		else
		{
			cfi_command(bank, 0xff, command);
			if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}

			LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
			return ERROR_FLASH_OPERATION_FAILED;
		}
	}

	cfi_command(bank, 0xff, command);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);

}

static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	u8 command[8];
	int i;

	for (i = first; i <= last; i++)
	{
		cfi_command(bank, 0xaa, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0x55, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0x80, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0xaa, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0x55, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_command(bank, 0x30, command);
		if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
			bank->sectors[i].is_erased = 1;
		else
		{
			cfi_command(bank, 0xf0, command);
			if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}

			LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
			return ERROR_FLASH_OPERATION_FAILED;
		}
	}

	cfi_command(bank, 0xf0, command);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}

static int cfi_erase(struct flash_bank_s *bank, int first, int last)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	if (bank->target->state != TARGET_HALTED)
	{
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if ((first < 0) || (last < first) || (last >= bank->num_sectors))
	{
		return ERROR_FLASH_SECTOR_INVALID;
	}

	if (cfi_info->qry[0] != 'Q')
		return ERROR_FLASH_BANK_NOT_PROBED;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			return cfi_intel_erase(bank, first, last);
			break;
		case 2:
			return cfi_spansion_erase(bank, first, last);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	return ERROR_OK;
}

static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	u8 command[8];
	int retry = 0;
	int i;

	/* if the device supports neither legacy lock/unlock (bit 3) nor
	 * instant individual block locking (bit 5).
	 */
	if (!(pri_ext->feature_support & 0x28))
		return ERROR_FLASH_OPERATION_FAILED;

	cfi_intel_clear_status_register(bank);

	for (i = first; i <= last; i++)
	{
		cfi_command(bank, 0x60, command);
		LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
		if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		if (set)
		{
			cfi_command(bank, 0x01, command);
			LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
			if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}
			bank->sectors[i].is_protected = 1;
		}
		else
		{
			cfi_command(bank, 0xd0, command);
			LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
			if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}
			bank->sectors[i].is_protected = 0;
		}

		/* instant individual block locking doesn't require reading of the status register */
		if (!(pri_ext->feature_support & 0x20))
		{
			/* Clear lock bits operation may take up to 1.4s */
			cfi_intel_wait_status_busy(bank, 1400);
		}
		else
		{
			u8 block_status;
			/* read block lock bit, to verify status */
			cfi_command(bank, 0x90, command);
			if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}
			block_status = cfi_get_u8(bank, i, 0x2);

			if ((block_status & 0x1) != set)
			{
				LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
				cfi_command(bank, 0x70, command);
				if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
				{
					return retval;
				}
				cfi_intel_wait_status_busy(bank, 10);

				if (retry > 10)
					return ERROR_FLASH_OPERATION_FAILED;
				else
				{
					i--;
					retry++;
				}
			}
		}
	}

	/* if the device doesn't support individual block lock bits set/clear,
	 * all blocks have been unlocked in parallel, so we set those that should be protected
	 */
	if ((!set) && (!(pri_ext->feature_support & 0x20)))
	{
		for (i = 0; i < bank->num_sectors; i++)
		{
			if (bank->sectors[i].is_protected == 1)
			{
				cfi_intel_clear_status_register(bank);

				cfi_command(bank, 0x60, command);
				if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
				{
					return retval;
				}

				cfi_command(bank, 0x01, command);
				if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
				{
					return retval;
				}

				cfi_intel_wait_status_busy(bank, 100);
			}
		}
	}

	cfi_command(bank, 0xff, command);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}

static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	if (bank->target->state != TARGET_HALTED)
	{
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if ((first < 0) || (last < first) || (last >= bank->num_sectors))
	{
		return ERROR_FLASH_SECTOR_INVALID;
	}

	if (cfi_info->qry[0] != 'Q')
		return ERROR_FLASH_BANK_NOT_PROBED;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			cfi_intel_protect(bank, set, first, last);
			break;
		default:
			LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	return ERROR_OK;
}

/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
{
	/* target_t *target = bank->target; */

	int i;

	/* NOTE:
	 * The data to flash must not be changed in endian! We write a bytestrem in
	 * target byte order already. Only the control and status byte lane of the flash
	 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
	 * word (data seems to be in the upper or lower byte lane for u16 accesses).
	 */

#if 0
	if (target->endianness == TARGET_LITTLE_ENDIAN)
	{
#endif
		/* shift bytes */
		for (i = 0; i < bank->bus_width - 1; i++)
			word[i] = word[i + 1];
		word[bank->bus_width - 1] = byte;
#if 0
	}
	else
	{
		/* shift bytes */
		for (i = bank->bus_width - 1; i > 0; i--)
			word[i] = word[i - 1];
		word[0] = byte;
	}
#endif
}

/* Convert code image to target endian */
/* FIXME create general block conversion fcts in target.c?) */
static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
{
	u32 i;
	for (i=0; i< count; i++)
	{
		target_buffer_set_u32(target, dest, *src);
		dest+=4;
		src++;
	}
}

static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
{
	target_t *target = bank->target;

	u8 buf[CFI_MAX_BUS_WIDTH];
	cfi_command(bank, cmd, buf);
	switch (bank->bus_width)
	{
	case 1 :
		return buf[0];
		break;
	case 2 :
		return target_buffer_get_u16(target, buf);
		break;
	case 4 :
		return target_buffer_get_u32(target, buf);
		break;
	default :
		LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
		return 0;
	}
}

static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	reg_param_t reg_params[7];
	armv4_5_algorithm_t armv4_5_info;
	working_area_t *source;
	u32 buffer_size = 32768;
	u32 write_command_val, busy_pattern_val, error_pattern_val;

	/* algorithm register usage:
	 * r0: source address (in RAM)
	 * r1: target address (in Flash)
	 * r2: count
	 * r3: flash write command
	 * r4: status byte (returned to host)
	 * r5: busy test pattern
	 * r6: error test pattern
	 */

	static const u32 word_32_code[] = {
		0xe4904004,   /* loop:	ldr r4, [r0], #4 */
		0xe5813000,   /* 		str r3, [r1] */
		0xe5814000,   /* 		str r4, [r1] */
		0xe5914000,   /* busy:  ldr r4, [r1] */
		0xe0047005,   /*		and r7, r4, r5 */
		0xe1570005,   /*		cmp r7, r5 */
		0x1afffffb,   /*		bne busy */
		0xe1140006,   /* 		tst r4, r6 */
		0x1a000003,   /*		bne done */
		0xe2522001,   /*		subs r2, r2, #1 */
		0x0a000001,   /* 		beq done */
		0xe2811004,   /*		add r1, r1 #4 */
		0xeafffff2,   /* 		b loop */
		0xeafffffe    /* done:	b -2 */
	};

	static const u32 word_16_code[] = {
		0xe0d040b2,   /* loop:	ldrh r4, [r0], #2 */
		0xe1c130b0,   /* 		strh r3, [r1] */
		0xe1c140b0,   /* 		strh r4, [r1] */
		0xe1d140b0,   /* busy	ldrh r4, [r1] */
		0xe0047005,   /*		and r7, r4, r5 */
		0xe1570005,   /*		cmp r7, r5 */
		0x1afffffb,   /*		bne busy */
		0xe1140006,   /* 		tst r4, r6 */
		0x1a000003,   /*		bne done */
		0xe2522001,   /*		subs r2, r2, #1 */
		0x0a000001,   /* 		beq done */
		0xe2811002,   /*		add r1, r1 #2 */
		0xeafffff2,   /* 		b loop */
		0xeafffffe    /* done:	b -2 */
	};

	static const u32 word_8_code[] = {
		0xe4d04001,   /* loop:	ldrb r4, [r0], #1 */
		0xe5c13000,   /* 		strb r3, [r1] */
		0xe5c14000,   /* 		strb r4, [r1] */
		0xe5d14000,   /* busy	ldrb r4, [r1] */
		0xe0047005,   /*		and r7, r4, r5 */
		0xe1570005,   /*		cmp r7, r5 */
		0x1afffffb,   /*		bne busy */
		0xe1140006,   /* 		tst r4, r6 */
		0x1a000003,   /*		bne done */
		0xe2522001,   /*		subs r2, r2, #1 */
		0x0a000001,   /* 		beq done */
		0xe2811001,   /*		add r1, r1 #1 */
		0xeafffff2,   /* 		b loop */
		0xeafffffe    /* done:	b -2 */
	};
	u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
	const u32 *target_code_src;
	u32 target_code_size;
	int retval = ERROR_OK;


	cfi_intel_clear_status_register(bank);

	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
	armv4_5_info.core_state = ARMV4_5_STATE_ARM;

	/* If we are setting up the write_algorith, we need target_code_src */
	/* if not we only need target_code_size.														*/
	/* 																																	*/
	/* However, we don't want to create multiple code paths, so we			*/
	/* do the unecessary evaluation of target_code_src, which the 			*/
	/* compiler will probably nicely optimize away if not needed				*/

	/* prepare algorithm code for target endian */
	switch (bank->bus_width)
	{
	case 1 :
		target_code_src = word_8_code;
		target_code_size = sizeof(word_8_code);
		break;
	case 2 :
		target_code_src = word_16_code;
		target_code_size = sizeof(word_16_code);
		break;
	case 4 :
		target_code_src = word_32_code;
		target_code_size = sizeof(word_32_code);
		break;
	default:
		LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
	}

	/* flash write code */
	if (!cfi_info->write_algorithm)
	{
		if ( target_code_size > sizeof(target_code) )
		{
			LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		}
		cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);

		/* Get memory for block write handler */
		retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
		if (retval != ERROR_OK)
		{
			LOG_WARNING("No working area available, can't do block memory writes");
			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		};

		/* write algorithm code to working area */
		retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
		if (retval != ERROR_OK)
		{
			LOG_ERROR("Unable to write block write code to target");
			goto cleanup;
		}
	}

	/* Get a workspace buffer for the data to flash starting with 32k size.
	   Half size until buffer would be smaller 256 Bytem then fail back */
	/* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
	{
		buffer_size /= 2;
		if (buffer_size <= 256)
		{
			LOG_WARNING("no large enough working area available, can't do block memory writes");
			retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
			goto cleanup;
		}
	};

	/* setup algo registers */
	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
	init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
	init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
	init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
	init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);

	/* prepare command and status register patterns */
	write_command_val = cfi_command_val(bank, 0x40);
	busy_pattern_val  = cfi_command_val(bank, 0x80);
	error_pattern_val = cfi_command_val(bank, 0x7e);

	LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );

	/* Programming main loop */
	while (count > 0)
	{
		u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
		u32 wsm_error;

		if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
		{
			goto cleanup;
		}

		buf_set_u32(reg_params[0].value, 0, 32, source->address);
		buf_set_u32(reg_params[1].value, 0, 32, address);
		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);

		buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
		buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
		buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);

		LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );

		/* Execute algorithm, assume breakpoint for last instruction */
		retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
			cfi_info->write_algorithm->address,
			cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
			10000, /* 10s should be enough for max. 32k of data */
			&armv4_5_info);

		/* On failure try a fall back to direct word writes */
		if (retval != ERROR_OK)
		{
			cfi_intel_clear_status_register(bank);
			LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
			retval = ERROR_FLASH_OPERATION_FAILED;
			/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
			/* FIXME To allow fall back or recovery, we must save the actual status
			   somewhere, so that a higher level code can start recovery. */
			goto cleanup;
		}

		/* Check return value from algo code */
		wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
		if (wsm_error)
		{
			/* read status register (outputs debug inforation) */
			cfi_intel_wait_status_busy(bank, 100);
			cfi_intel_clear_status_register(bank);
			retval = ERROR_FLASH_OPERATION_FAILED;
			goto cleanup;
		}

		buffer += thisrun_count;
		address += thisrun_count;
		count -= thisrun_count;
	}

	/* free up resources */
cleanup:
	if (source)
		target_free_working_area(target, source);

	if (cfi_info->write_algorithm)
	{
		target_free_working_area(target, cfi_info->write_algorithm);
		cfi_info->write_algorithm = NULL;
	}

	destroy_reg_param(&reg_params[0]);
	destroy_reg_param(&reg_params[1]);
	destroy_reg_param(&reg_params[2]);
	destroy_reg_param(&reg_params[3]);
	destroy_reg_param(&reg_params[4]);
	destroy_reg_param(&reg_params[5]);
	destroy_reg_param(&reg_params[6]);

	return retval;
}

static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	reg_param_t reg_params[10];
	armv4_5_algorithm_t armv4_5_info;
	working_area_t *source;
	u32 buffer_size = 32768;
	u32 status;
	int retval, retvaltemp;
	int exit_code = ERROR_OK;

	/* input parameters - */
	/*	R0 = source address */
	/*	R1 = destination address */
	/*	R2 = number of writes */
	/*	R3 = flash write command */
	/*	R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
	/* output parameters - */
	/*	R5 = 0x80 ok 0x00 bad */
	/* temp registers - */
	/*	R6 = value read from flash to test status */
	/*	R7 = holding register */
	/* unlock registers - */
	/*  R8 = unlock1_addr */
	/*  R9 = unlock1_cmd */
	/*  R10 = unlock2_addr */
	/*  R11 = unlock2_cmd */

	static const u32 word_32_code[] = {
						/* 00008100 <sp_32_code>:		*/
		0xe4905004,		/* ldr	r5, [r0], #4			*/
		0xe5889000, 	/* str	r9, [r8]				*/
		0xe58ab000, 	/* str	r11, [r10]				*/
		0xe5883000, 	/* str	r3, [r8]				*/
		0xe5815000, 	/* str	r5, [r1]				*/
		0xe1a00000, 	/* nop							*/
						/*								*/
						/* 00008110 <sp_32_busy>:		*/
		0xe5916000, 	/* ldr	r6, [r1]				*/
		0xe0257006, 	/* eor	r7, r5, r6				*/
		0xe0147007, 	/* ands	r7, r4, r7				*/
		0x0a000007, 	/* beq	8140 <sp_32_cont> ; b if DQ7 == Data7 */
		0xe0166124, 	/* ands	r6, r6, r4, lsr #2		*/
		0x0afffff9, 	/* beq	8110 <sp_32_busy> ;	b if DQ5 low */
		0xe5916000, 	/* ldr	r6, [r1]				*/
		0xe0257006, 	/* eor	r7, r5, r6				*/
		0xe0147007, 	/* ands	r7, r4, r7				*/
		0x0a000001, 	/* beq	8140 <sp_32_cont> ; b if DQ7 == Data7 */
		0xe3a05000, 	/* mov	r5, #0	; 0x0 - return 0x00, error */
		0x1a000004, 	/* bne	8154 <sp_32_done>		*/
						/*								*/
				/* 00008140 <sp_32_cont>:				*/
		0xe2522001, 	/* subs	r2, r2, #1	; 0x1		*/
		0x03a05080, 	/* moveq	r5, #128	; 0x80	*/
		0x0a000001, 	/* beq	8154 <sp_32_done>		*/
		0xe2811004, 	/* add	r1, r1, #4	; 0x4		*/
		0xeaffffe8, 	/* b	8100 <sp_32_code>		*/
						/*								*/
						/* 00008154 <sp_32_done>:		*/
		0xeafffffe		/* b	8154 <sp_32_done>		*/
		};

		static const u32 word_16_code[] = {
				/* 00008158 <sp_16_code>:              */
		0xe0d050b2, 	/* ldrh	r5, [r0], #2		   */
		0xe1c890b0, 	/* strh	r9, [r8]				*/
		0xe1cab0b0, 	/* strh	r11, [r10]				*/
		0xe1c830b0, 	/* strh	r3, [r8]				*/
		0xe1c150b0, 	/* strh	r5, [r1]		       */
		0xe1a00000, 	/* nop			(mov r0,r0)    */
				/* 				       */
				/* 00008168 <sp_16_busy>:	       */
		0xe1d160b0, 	/* ldrh	r6, [r1]		       */
		0xe0257006, 	/* eor	r7, r5, r6		       */
		0xe0147007, 	/* ands	r7, r4, r7		       */
		0x0a000007, 	/* beq	8198 <sp_16_cont>	       */
		0xe0166124, 	/* ands	r6, r6, r4, lsr #2	       */
		0x0afffff9, 	/* beq	8168 <sp_16_busy>	       */
		0xe1d160b0, 	/* ldrh	r6, [r1]		       */
		0xe0257006, 	/* eor	r7, r5, r6		       */
		0xe0147007, 	/* ands	r7, r4, r7		       */
		0x0a000001, 	/* beq	8198 <sp_16_cont>	       */
		0xe3a05000, 	/* mov	r5, #0	; 0x0		       */
		0x1a000004, 	/* bne	81ac <sp_16_done>	       */
				/* 				       */
				/* 00008198 <sp_16_cont>:	       */
		0xe2522001, 	/* subs	r2, r2, #1	; 0x1	       */
		0x03a05080, 	/* moveq	r5, #128	; 0x80 */
		0x0a000001, 	/* beq	81ac <sp_16_done>	       */
		0xe2811002, 	/* add	r1, r1, #2	; 0x2	       */
		0xeaffffe8, 	/* b	8158 <sp_16_code>	       */
				/* 				       */
				/* 000081ac <sp_16_done>:	       */
		0xeafffffe 	/* b	81ac <sp_16_done>              */
		};

		static const u32 word_8_code[] = {
				/* 000081b0 <sp_16_code_end>:          */
		0xe4d05001, 	/* ldrb	r5, [r0], #1		       */
		0xe5c89000, 	/* strb	r9, [r8]				*/
		0xe5cab000, 	/* strb	r11, [r10]				*/
		0xe5c83000, 	/* strb	r3, [r8]				*/
		0xe5c15000, 	/* strb	r5, [r1]		       */
		0xe1a00000, 	/* nop			(mov r0,r0)    */
				/* 				       */
				/* 000081c0 <sp_8_busy>:	       */
		0xe5d16000, 	/* ldrb	r6, [r1]		       */
		0xe0257006, 	/* eor	r7, r5, r6		       */
		0xe0147007, 	/* ands	r7, r4, r7		       */
		0x0a000007, 	/* beq	81f0 <sp_8_cont>	       */
		0xe0166124, 	/* ands	r6, r6, r4, lsr #2	       */
		0x0afffff9, 	/* beq	81c0 <sp_8_busy>	       */
		0xe5d16000, 	/* ldrb	r6, [r1]		       */
		0xe0257006, 	/* eor	r7, r5, r6		       */
		0xe0147007, 	/* ands	r7, r4, r7		       */
		0x0a000001, 	/* beq	81f0 <sp_8_cont>	       */
		0xe3a05000, 	/* mov	r5, #0	; 0x0		       */
		0x1a000004, 	/* bne	8204 <sp_8_done>	       */
				/* 				       */
				/* 000081f0 <sp_8_cont>:	       */
		0xe2522001, 	/* subs	r2, r2, #1	; 0x1	       */
		0x03a05080, 	/* moveq	r5, #128	; 0x80 */
		0x0a000001, 	/* beq	8204 <sp_8_done>	       */
		0xe2811001, 	/* add	r1, r1, #1	; 0x1	       */
		0xeaffffe8, 	/* b	81b0 <sp_16_code_end>	       */
				/* 				       */
				/* 00008204 <sp_8_done>:	       */
		0xeafffffe 	/* b	8204 <sp_8_done>               */
	};

	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
	armv4_5_info.core_state = ARMV4_5_STATE_ARM;

	/* flash write code */
	if (!cfi_info->write_algorithm)
	{
		u8 *target_code;
		int target_code_size;
		const u32 *src;

		/* convert bus-width dependent algorithm code to correct endiannes */
		switch (bank->bus_width)
		{
		case 1:
			src = word_8_code;
			target_code_size = sizeof(word_8_code);
			break;
		case 2:
			src = word_16_code;
			target_code_size = sizeof(word_16_code);
			break;
		case 4:
			src = word_32_code;
			target_code_size = sizeof(word_32_code);
			break;
		default:
			LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
			return ERROR_FLASH_OPERATION_FAILED;
		}
		target_code = malloc(target_code_size);
		cfi_fix_code_endian(target, target_code, src, target_code_size / 4);

		/* allocate working area */
		retval=target_alloc_working_area(target, target_code_size,
				&cfi_info->write_algorithm);
		if (retval != ERROR_OK)
		{
			free(target_code);
			return retval;
		}

		/* write algorithm code to working area */
		if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
		                    target_code_size, target_code)) != ERROR_OK)
		{
			free(target_code);
			return retval;
		}

		free(target_code);
	}
	/* the following code still assumes target code is fixed 24*4 bytes */

	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
	{
		buffer_size /= 2;
		if (buffer_size <= 256)
		{
			/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
			if (cfi_info->write_algorithm)
				target_free_working_area(target, cfi_info->write_algorithm);

			LOG_WARNING("not enough working area available, can't do block memory writes");
			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
		}
	};

	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
	init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
	init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
	init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
	init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
	init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
	init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
	init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);

	while (count > 0)
	{
		u32 thisrun_count = (count > buffer_size) ? buffer_size : count;

		retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);

		buf_set_u32(reg_params[0].value, 0, 32, source->address);
		buf_set_u32(reg_params[1].value, 0, 32, address);
		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
		buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
		buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
		buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
		buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
		buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
		buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);

		retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
						     cfi_info->write_algorithm->address,
						     cfi_info->write_algorithm->address + ((24 * 4) - 4),
						     10000, &armv4_5_info);

		status = buf_get_u32(reg_params[5].value, 0, 32);

		if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
		{
			LOG_DEBUG("status: 0x%x", status);
			exit_code = ERROR_FLASH_OPERATION_FAILED;
			break;
		}

		buffer += thisrun_count;
		address += thisrun_count;
		count -= thisrun_count;
	}

	target_free_working_area(target, source);

	destroy_reg_param(&reg_params[0]);
	destroy_reg_param(&reg_params[1]);
	destroy_reg_param(&reg_params[2]);
	destroy_reg_param(&reg_params[3]);
	destroy_reg_param(&reg_params[4]);
	destroy_reg_param(&reg_params[5]);
	destroy_reg_param(&reg_params[6]);
	destroy_reg_param(&reg_params[7]);
	destroy_reg_param(&reg_params[8]);
	destroy_reg_param(&reg_params[9]);

	return exit_code;
}

static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u8 command[8];

	cfi_intel_clear_status_register(bank);
	cfi_command(bank, 0x40, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
	{
		return retval;
	}

	if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
	{
		cfi_command(bank, 0xff, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	return ERROR_OK;
}

static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u8 command[8];

	/* Calculate buffer size and boundary mask */
	u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
	u32 buffermask = buffersize-1;
	u32 bufferwsize;

	/* Check for valid range */
	if (address & buffermask)
	{
		LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
		return ERROR_FLASH_OPERATION_FAILED;
	}
	switch(bank->chip_width)
	{
	case 4 : bufferwsize = buffersize / 4; break;
	case 2 : bufferwsize = buffersize / 2; break;
	case 1 : bufferwsize = buffersize; break;
	default:
		LOG_ERROR("Unsupported chip width %d", bank->chip_width);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	bufferwsize/=(bank->bus_width / bank->chip_width);


	/* Check for valid size */
	if (wordcount > bufferwsize)
	{
		LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	/* Write to flash buffer */
	cfi_intel_clear_status_register(bank);

	/* Initiate buffer operation _*/
	cfi_command(bank, 0xE8, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}
	if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
	{
		cfi_command(bank, 0xff, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	/* Write buffer wordcount-1 and data words */
	cfi_command(bank, bufferwsize-1, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
	{
		return retval;
	}

	/* Commit write operation */
	cfi_command(bank, 0xd0, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}
	if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
	{
		cfi_command(bank, 0xff, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	return ERROR_OK;
}

static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	u8 command[8];

	cfi_command(bank, 0xaa, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	cfi_command(bank, 0x55, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	cfi_command(bank, 0xa0, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
	{
		return retval;
	}

	if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
	{
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	return ERROR_OK;
}

static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u8 command[8];
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;

	/* Calculate buffer size and boundary mask */
	u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
	u32 buffermask = buffersize-1;
	u32 bufferwsize;

	/* Check for valid range */
	if (address & buffermask)
	{
		LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
		return ERROR_FLASH_OPERATION_FAILED;
	}
	switch(bank->chip_width)
	{
	case 4 : bufferwsize = buffersize / 4; break;
	case 2 : bufferwsize = buffersize / 2; break;
	case 1 : bufferwsize = buffersize; break;
	default:
		LOG_ERROR("Unsupported chip width %d", bank->chip_width);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	bufferwsize/=(bank->bus_width / bank->chip_width);

	/* Check for valid size */
	if (wordcount > bufferwsize)
	{
		LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	// Unlock
	cfi_command(bank, 0xaa, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	cfi_command(bank, 0x55, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	// Buffer load command
	cfi_command(bank, 0x25, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	/* Write buffer wordcount-1 and data words */
	cfi_command(bank, bufferwsize-1, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
	{
		return retval;
	}

	/* Commit write operation */
	cfi_command(bank, 0x29, command);
	if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
	{
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
		return ERROR_FLASH_OPERATION_FAILED;
	}

	return ERROR_OK;
}

static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			return cfi_intel_write_word(bank, word, address);
			break;
		case 2:
			return cfi_spansion_write_word(bank, word, address);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	return ERROR_FLASH_OPERATION_FAILED;
}

static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			return cfi_intel_write_words(bank, word, wordcount, address);
			break;
		case 2:
			return cfi_spansion_write_words(bank, word, wordcount, address);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	return ERROR_FLASH_OPERATION_FAILED;
}

int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u32 address = bank->base + offset;	/* address of first byte to be programmed */
	u32 write_p, copy_p;
	int align;	/* number of unaligned bytes */
	int blk_count; /* number of bus_width bytes for block copy */
	u8 current_word[CFI_MAX_BUS_WIDTH * 4];	/* word (bus_width size) currently being programmed */
	int i;
	int retval;

	if (bank->target->state != TARGET_HALTED)
	{
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if (offset + count > bank->size)
		return ERROR_FLASH_DST_OUT_OF_BANK;

	if (cfi_info->qry[0] != 'Q')
		return ERROR_FLASH_BANK_NOT_PROBED;

	/* start at the first byte of the first word (bus_width size) */
	write_p = address & ~(bank->bus_width - 1);
	if ((align = address - write_p) != 0)
	{
		LOG_INFO("Fixup %d unaligned head bytes", align );

		for (i = 0; i < bank->bus_width; i++)
			current_word[i] = 0;
		copy_p = write_p;

		/* copy bytes before the first write address */
		for (i = 0; i < align; ++i, ++copy_p)
		{
			u8 byte;
			if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
			{
				return retval;
			}
			cfi_add_byte(bank, current_word, byte);
		}

		/* add bytes from the buffer */
		for (; (i < bank->bus_width) && (count > 0); i++)
		{
			cfi_add_byte(bank, current_word, *buffer++);
			count--;
			copy_p++;
		}

		/* if the buffer is already finished, copy bytes after the last write address */
		for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
		{
			u8 byte;
			if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
			{
				return retval;
			}
			cfi_add_byte(bank, current_word, byte);
		}

		retval = cfi_write_word(bank, current_word, write_p);
		if (retval != ERROR_OK)
			return retval;
		write_p = copy_p;
	}

	/* handle blocks of bus_size aligned bytes */
	blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
	switch(cfi_info->pri_id)
	{
		/* try block writes (fails without working area) */
		case 1:
		case 3:
			retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
			break;
		case 2:
			retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			retval = ERROR_FLASH_OPERATION_FAILED;
			break;
	}
	if (retval == ERROR_OK)
	{
		/* Increment pointers and decrease count on succesful block write */
		buffer += blk_count;
		write_p += blk_count;
		count -= blk_count;
	}
	else
	{
		if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
		{
			//adjust buffersize for chip width
			u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
			u32 buffermask = buffersize-1;
			u32 bufferwsize;

			switch(bank->chip_width)
			{
			case 4 : bufferwsize = buffersize / 4; break;
			case 2 : bufferwsize = buffersize / 2; break;
			case 1 : bufferwsize = buffersize; break;
			default:
				LOG_ERROR("Unsupported chip width %d", bank->chip_width);
				return ERROR_FLASH_OPERATION_FAILED;
			}

			bufferwsize/=(bank->bus_width / bank->chip_width);

			/* fall back to memory writes */
			while (count >= (u32)bank->bus_width)
			{
				int fallback;
				if ((write_p & 0xff) == 0)
				{
					LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
				}
				fallback = 1;
				if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
				{
					retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
					if (retval == ERROR_OK)
					{
						buffer += buffersize;
						write_p += buffersize;
						count -= buffersize;
						fallback=0;
					}
				}
				/* try the slow way? */
				if (fallback)
				{
					for (i = 0; i < bank->bus_width; i++)
						current_word[i] = 0;

					for (i = 0; i < bank->bus_width; i++)
					{
						cfi_add_byte(bank, current_word, *buffer++);
					}

					retval = cfi_write_word(bank, current_word, write_p);
					if (retval != ERROR_OK)
						return retval;

					write_p += bank->bus_width;
					count -= bank->bus_width;
				}
			}
		}
		else
			return retval;
	}

	/* return to read array mode, so we can read from flash again for padding */
	cfi_command(bank, 0xf0, current_word);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
	{
		return retval;
	}
	cfi_command(bank, 0xff, current_word);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
	{
		return retval;
	}

	/* handle unaligned tail bytes */
	if (count > 0)
	{
		LOG_INFO("Fixup %d unaligned tail bytes", count );

		copy_p = write_p;
		for (i = 0; i < bank->bus_width; i++)
			current_word[i] = 0;

		for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
		{
			cfi_add_byte(bank, current_word, *buffer++);
			count--;
		}
		for (; i < bank->bus_width; ++i, ++copy_p)
		{
			u8 byte;
			if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
			{
				return retval;
			}
			cfi_add_byte(bank, current_word, byte);
		}
		retval = cfi_write_word(bank, current_word, write_p);
		if (retval != ERROR_OK)
			return retval;
	}

	/* return to read array mode */
	cfi_command(bank, 0xf0, current_word);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
	{
		return retval;
	}
	cfi_command(bank, 0xff, current_word);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
}

static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
{
	(void) param;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;

	pri_ext->_reversed_geometry = 1;
}

static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
{
	int i;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	(void) param;

	if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
	{
		LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");

		for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
		{
			int j = (cfi_info->num_erase_regions - 1) - i;
			u32 swap;

			swap = cfi_info->erase_region_info[i];
			cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
			cfi_info->erase_region_info[j] = swap;
		}
	}
}

static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	cfi_unlock_addresses_t *unlock_addresses = param;

	pri_ext->_unlock1 = unlock_addresses->unlock1;
	pri_ext->_unlock2 = unlock_addresses->unlock2;
}

static int cfi_probe(struct flash_bank_s *bank)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	target_t *target = bank->target;
	u8 command[8];
	int num_sectors = 0;
	int i;
	int sector = 0;
	u32 unlock1 = 0x555;
	u32 unlock2 = 0x2aa;
	int retval;

	if (bank->target->state != TARGET_HALTED)
	{
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	cfi_info->probed = 0;

	/* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
	 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
	 */
	if (cfi_info->jedec_probe)
	{
		unlock1 = 0x5555;
		unlock2 = 0x2aaa;
	}

	/* switch to read identifier codes mode ("AUTOSELECT") */
	cfi_command(bank, 0xaa, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}
	cfi_command(bank, 0x55, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}
	cfi_command(bank, 0x90, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	if (bank->chip_width == 1)
	{
		u8 manufacturer, device_id;
		if((retval = target_read_u8(target, bank->base + 0x0, &manufacturer)) != ERROR_OK)
		{
			return retval;
		}
		if((retval = target_read_u8(target, bank->base + 0x1, &device_id)) != ERROR_OK)
		{
			return retval;
		}
		cfi_info->manufacturer = manufacturer;
		cfi_info->device_id = device_id;
	}
	else if (bank->chip_width == 2)
	{
		if((retval = target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer)) != ERROR_OK)
		{
			return retval;
		}
		if((retval = target_read_u16(target, bank->base + 0x2, &cfi_info->device_id)) != ERROR_OK)
		{
			return retval;
		}
	}

	LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
	/* switch back to read array mode */
	cfi_command(bank, 0xf0, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}
	cfi_command(bank, 0xff, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	/* check device/manufacturer ID for known non-CFI flashes. */
	cfi_fixup_non_cfi(bank);

	/* query only if this is a CFI compatible flash,
	 * otherwise the relevant info has already been filled in
	 */
	if (cfi_info->not_cfi == 0)
	{
		/* enter CFI query mode
		 * according to JEDEC Standard No. 68.01,
		 * a single bus sequence with address = 0x55, data = 0x98 should put
		 * the device into CFI query mode.
		 *
		 * SST flashes clearly violate this, and we will consider them incompatbile for now
		 */
		cfi_command(bank, 0x98, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}

		cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
		cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
		cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);

		LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);

		if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
		{
			cfi_command(bank, 0xf0, command);
			if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}
			cfi_command(bank, 0xff, command);
			if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
			{
				return retval;
			}
			LOG_ERROR("Could not probe bank: no QRY");
			return ERROR_FLASH_BANK_INVALID;
		}

		cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
		cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
		cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
		cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);

		LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);

		cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
		cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
		cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
		cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
		cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
		cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
		cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
		cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
		cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
		cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
		cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
		cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);

		LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
			(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
			(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
			(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
			(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
		LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
			1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
		LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
			(1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
			(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
			(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));

		cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
		cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
		cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
		cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);

		LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));

		if (cfi_info->num_erase_regions)
		{
			cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
			for (i = 0; i < cfi_info->num_erase_regions; i++)
			{
				cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
				LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
			}
		}
		else
		{
			cfi_info->erase_region_info = NULL;
		}

		/* We need to read the primary algorithm extended query table before calculating
		 * the sector layout to be able to apply fixups
		 */
		switch(cfi_info->pri_id)
		{
			/* Intel command set (standard and extended) */
			case 0x0001:
			case 0x0003:
				cfi_read_intel_pri_ext(bank);
				break;
			/* AMD/Spansion, Atmel, ... command set */
			case 0x0002:
				cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
				cfi_read_0002_pri_ext(bank);
				break;
			default:
				LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
				break;
		}

		/* return to read array mode
		 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
		 */
		cfi_command(bank, 0xf0, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
		cfi_command(bank, 0xff, command);
		if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
		{
			return retval;
		}
	} /* end CFI case */

	/* apply fixups depending on the primary command set */
	switch(cfi_info->pri_id)
	{
		/* Intel command set (standard and extended) */
		case 0x0001:
		case 0x0003:
			cfi_fixup(bank, cfi_0001_fixups);
			break;
		/* AMD/Spansion, Atmel, ... command set */
		case 0x0002:
			cfi_fixup(bank, cfi_0002_fixups);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
	{
		LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
	}

	if (cfi_info->num_erase_regions == 0)
	{
		/* a device might have only one erase block, spanning the whole device */
		bank->num_sectors = 1;
		bank->sectors = malloc(sizeof(flash_sector_t));

		bank->sectors[sector].offset = 0x0;
		bank->sectors[sector].size = bank->size;
		bank->sectors[sector].is_erased = -1;
		bank->sectors[sector].is_protected = -1;
	}
	else
	{
		u32 offset = 0;

		for (i = 0; i < cfi_info->num_erase_regions; i++)
		{
			num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
		}

		bank->num_sectors = num_sectors;
		bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);

		for (i = 0; i < cfi_info->num_erase_regions; i++)
		{
			u32 j;
			for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
			{
				bank->sectors[sector].offset = offset;
				bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
				offset += bank->sectors[sector].size;
				bank->sectors[sector].is_erased = -1;
				bank->sectors[sector].is_protected = -1;
				sector++;
			}
		}
		if (offset != cfi_info->dev_size)
		{
			LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
		}
	}

	cfi_info->probed = 1;

	return ERROR_OK;
}

static int cfi_auto_probe(struct flash_bank_s *bank)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	if (cfi_info->probed)
		return ERROR_OK;
	return cfi_probe(bank);
}


static int cfi_intel_protect_check(struct flash_bank_s *bank)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	u8 command[CFI_MAX_BUS_WIDTH];
	int i;

	/* check if block lock bits are supported on this device */
	if (!(pri_ext->blk_status_reg_mask & 0x1))
		return ERROR_FLASH_OPERATION_FAILED;

	cfi_command(bank, 0x90, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	for (i = 0; i < bank->num_sectors; i++)
	{
		u8 block_status = cfi_get_u8(bank, i, 0x2);

		if (block_status & 1)
			bank->sectors[i].is_protected = 1;
		else
			bank->sectors[i].is_protected = 0;
	}

	cfi_command(bank, 0xff, command);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}

static int cfi_spansion_protect_check(struct flash_bank_s *bank)
{
	int retval;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;
	cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
	target_t *target = bank->target;
	u8 command[8];
	int i;

	cfi_command(bank, 0xaa, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	cfi_command(bank, 0x55, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	cfi_command(bank, 0x90, command);
	if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
	{
		return retval;
	}

	for (i = 0; i < bank->num_sectors; i++)
	{
		u8 block_status = cfi_get_u8(bank, i, 0x2);

		if (block_status & 1)
			bank->sectors[i].is_protected = 1;
		else
			bank->sectors[i].is_protected = 0;
	}

	cfi_command(bank, 0xf0, command);
	return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}

static int cfi_protect_check(struct flash_bank_s *bank)
{
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	if (bank->target->state != TARGET_HALTED)
	{
		LOG_ERROR("Target not halted");
		return ERROR_TARGET_NOT_HALTED;
	}

	if (cfi_info->qry[0] != 'Q')
		return ERROR_FLASH_BANK_NOT_PROBED;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			return cfi_intel_protect_check(bank);
			break;
		case 2:
			return cfi_spansion_protect_check(bank);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}

	return ERROR_OK;
}

static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
	int printed;
	cfi_flash_bank_t *cfi_info = bank->driver_priv;

	if (cfi_info->qry[0] == (char)-1)
	{
		printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
		return ERROR_OK;
	}

	if (cfi_info->not_cfi == 0)
		printed = snprintf(buf, buf_size, "\ncfi information:\n");
	else
		printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
	buf += printed;
	buf_size -= printed;

	printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
		cfi_info->manufacturer, cfi_info->device_id);
	buf += printed;
	buf_size -= printed;

	if (cfi_info->not_cfi == 0)
	{
	printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
	buf += printed;
	buf_size -= printed;

		printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
		                   (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
	(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
	(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
	(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
	buf += printed;
	buf_size -= printed;

		printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
		                   1 << cfi_info->word_write_timeout_typ,
		                   1 << cfi_info->buf_write_timeout_typ,
		                   1 << cfi_info->block_erase_timeout_typ,
		                   1 << cfi_info->chip_erase_timeout_typ);
	buf += printed;
	buf_size -= printed;

		printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
		                   (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
		  (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
		  (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
		  (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
	buf += printed;
	buf_size -= printed;

		printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
		                   cfi_info->dev_size,
		                   cfi_info->interface_desc,
		                   1 << cfi_info->max_buf_write_size);
	buf += printed;
	buf_size -= printed;

	switch(cfi_info->pri_id)
	{
		case 1:
		case 3:
			cfi_intel_info(bank, buf, buf_size);
			break;
		case 2:
			cfi_spansion_info(bank, buf, buf_size);
			break;
		default:
			LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
			break;
	}
	}

	return ERROR_OK;
}
'#n2212'>2212</a>
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<a id='n2412' href='#n2412'>2412</a>
<a id='n2413' href='#n2413'>2413</a>
<a id='n2414' href='#n2414'>2414</a>
<a id='n2415' href='#n2415'>2415</a>
<a id='n2416' href='#n2416'>2416</a>
<a id='n2417' href='#n2417'>2417</a>
<a id='n2418' href='#n2418'>2418</a>
<a id='n2419' href='#n2419'>2419</a>
<a id='n2420' href='#n2420'>2420</a>
<a id='n2421' href='#n2421'>2421</a>
<a id='n2422' href='#n2422'>2422</a>
<a id='n2423' href='#n2423'>2423</a>
<a id='n2424' href='#n2424'>2424</a>
<a id='n2425' href='#n2425'>2425</a>
<a id='n2426' href='#n2426'>2426</a>
<a id='n2427' href='#n2427'>2427</a>
<a id='n2428' href='#n2428'>2428</a>
<a id='n2429' href='#n2429'>2429</a>
<a id='n2430' href='#n2430'>2430</a>
<a id='n2431' href='#n2431'>2431</a>
<a id='n2432' href='#n2432'>2432</a>
<a id='n2433' href='#n2433'>2433</a>
<a id='n2434' href='#n2434'>2434</a>
<a id='n2435' href='#n2435'>2435</a>
<a id='n2436' href='#n2436'>2436</a>
<a id='n2437' href='#n2437'>2437</a>
<a id='n2438' href='#n2438'>2438</a>
<a id='n2439' href='#n2439'>2439</a>
<a id='n2440' href='#n2440'>2440</a>
<a id='n2441' href='#n2441'>2441</a>
<a id='n2442' href='#n2442'>2442</a>
<a id='n2443' href='#n2443'>2443</a>
<a id='n2444' href='#n2444'>2444</a>
<a id='n2445' href='#n2445'>2445</a>
<a id='n2446' href='#n2446'>2446</a>
<a id='n2447' href='#n2447'>2447</a>
<a id='n2448' href='#n2448'>2448</a>
<a id='n2449' href='#n2449'>2449</a>
<a id='n2450' href='#n2450'>2450</a>
<a id='n2451' href='#n2451'>2451</a>
<a id='n2452' href='#n2452'>2452</a>
<a id='n2453' href='#n2453'>2453</a>
<a id='n2454' href='#n2454'>2454</a>
<a id='n2455' href='#n2455'>2455</a>
<a id='n2456' href='#n2456'>2456</a>
<a id='n2457' href='#n2457'>2457</a>
<a id='n2458' href='#n2458'>2458</a>
<a id='n2459' href='#n2459'>2459</a>
<a id='n2460' href='#n2460'>2460</a>
<a id='n2461' href='#n2461'>2461</a>
<a id='n2462' href='#n2462'>2462</a>
<a id='n2463' href='#n2463'>2463</a>
<a id='n2464' href='#n2464'>2464</a>
<a id='n2465' href='#n2465'>2465</a>
<a id='n2466' href='#n2466'>2466</a>
<a id='n2467' href='#n2467'>2467</a>
<a id='n2468' href='#n2468'>2468</a>
<a id='n2469' href='#n2469'>2469</a>
<a id='n2470' href='#n2470'>2470</a>
<a id='n2471' href='#n2471'>2471</a>
<a id='n2472' href='#n2472'>2472</a>
<a id='n2473' href='#n2473'>2473</a>
<a id='n2474' href='#n2474'>2474</a>
<a id='n2475' href='#n2475'>2475</a>
<a id='n2476' href='#n2476'>2476</a>
<a id='n2477' href='#n2477'>2477</a>
<a id='n2478' href='#n2478'>2478</a>
<a id='n2479' href='#n2479'>2479</a>
<a id='n2480' href='#n2480'>2480</a>
<a id='n2481' href='#n2481'>2481</a>
<a id='n2482' href='#n2482'>2482</a>
<a id='n2483' href='#n2483'>2483</a>
<a id='n2484' href='#n2484'>2484</a>
<a id='n2485' href='#n2485'>2485</a>
<a id='n2486' href='#n2486'>2486</a>
<a id='n2487' href='#n2487'>2487</a>
<a id='n2488' href='#n2488'>2488</a>
<a id='n2489' href='#n2489'>2489</a>
<a id='n2490' href='#n2490'>2490</a>
<a id='n2491' href='#n2491'>2491</a>
<a id='n2492' href='#n2492'>2492</a>
<a id='n2493' href='#n2493'>2493</a>
<a id='n2494' href='#n2494'>2494</a>
<a id='n2495' href='#n2495'>2495</a>
<a id='n2496' href='#n2496'>2496</a>
<a id='n2497' href='#n2497'>2497</a>
<a id='n2498' href='#n2498'>2498</a>
<a id='n2499' href='#n2499'>2499</a>
<a id='n2500' href='#n2500'>2500</a>
<a id='n2501' href='#n2501'>2501</a>
<a id='n2502' href='#n2502'>2502</a>
<a id='n2503' href='#n2503'>2503</a>
<a id='n2504' href='#n2504'>2504</a>
<a id='n2505' href='#n2505'>2505</a>
<a id='n2506' href='#n2506'>2506</a>
<a id='n2507' href='#n2507'>2507</a>
<a id='n2508' href='#n2508'>2508</a>
<a id='n2509' href='#n2509'>2509</a>
<a id='n2510' href='#n2510'>2510</a>
<a id='n2511' href='#n2511'>2511</a>
<a id='n2512' href='#n2512'>2512</a>
<a id='n2513' href='#n2513'>2513</a>
<a id='n2514' href='#n2514'>2514</a>
<a id='n2515' href='#n2515'>2515</a>
<a id='n2516' href='#n2516'>2516</a>
<a id='n2517' href='#n2517'>2517</a>
<a id='n2518' href='#n2518'>2518</a>
<a id='n2519' href='#n2519'>2519</a>
<a id='n2520' href='#n2520'>2520</a>
<a id='n2521' href='#n2521'>2521</a>
<a id='n2522' href='#n2522'>2522</a>
<a id='n2523' href='#n2523'>2523</a>
<a id='n2524' href='#n2524'>2524</a>
<a id='n2525' href='#n2525'>2525</a>
<a id='n2526' href='#n2526'>2526</a>
<a id='n2527' href='#n2527'>2527</a>
<a id='n2528' href='#n2528'>2528</a>
<a id='n2529' href='#n2529'>2529</a>
<a id='n2530' href='#n2530'>2530</a>
<a id='n2531' href='#n2531'>2531</a>
<a id='n2532' href='#n2532'>2532</a>
<a id='n2533' href='#n2533'>2533</a>
<a id='n2534' href='#n2534'>2534</a>
<a id='n2535' href='#n2535'>2535</a>
<a id='n2536' href='#n2536'>2536</a>
<a id='n2537' href='#n2537'>2537</a>
<a id='n2538' href='#n2538'>2538</a>
<a id='n2539' href='#n2539'>2539</a>
<a id='n2540' href='#n2540'>2540</a>
<a id='n2541' href='#n2541'>2541</a>
<a id='n2542' href='#n2542'>2542</a>
<a id='n2543' href='#n2543'>2543</a>
<a id='n2544' href='#n2544'>2544</a>
<a id='n2545' href='#n2545'>2545</a>
<a id='n2546' href='#n2546'>2546</a>
<a id='n2547' href='#n2547'>2547</a>
<a id='n2548' href='#n2548'>2548</a>
<a id='n2549' href='#n2549'>2549</a>
<a id='n2550' href='#n2550'>2550</a>
<a id='n2551' href='#n2551'>2551</a>
<a id='n2552' href='#n2552'>2552</a>
<a id='n2553' href='#n2553'>2553</a>
<a id='n2554' href='#n2554'>2554</a>
<a id='n2555' href='#n2555'>2555</a>
<a id='n2556' href='#n2556'>2556</a>
<a id='n2557' href='#n2557'>2557</a>
<a id='n2558' href='#n2558'>2558</a>
<a id='n2559' href='#n2559'>2559</a>
<a id='n2560' href='#n2560'>2560</a>
<a id='n2561' href='#n2561'>2561</a>
<a id='n2562' href='#n2562'>2562</a>
<a id='n2563' href='#n2563'>2563</a>
<a id='n2564' href='#n2564'>2564</a>
<a id='n2565' href='#n2565'>2565</a>
<a id='n2566' href='#n2566'>2566</a>
<a id='n2567' href='#n2567'>2567</a>
<a id='n2568' href='#n2568'>2568</a>
<a id='n2569' href='#n2569'>2569</a>
<a id='n2570' href='#n2570'>2570</a>
<a id='n2571' href='#n2571'>2571</a>
<a id='n2572' href='#n2572'>2572</a>
<a id='n2573' href='#n2573'>2573</a>
<a id='n2574' href='#n2574'>2574</a>
<a id='n2575' href='#n2575'>2575</a>
<a id='n2576' href='#n2576'>2576</a>
<a id='n2577' href='#n2577'>2577</a>
<a id='n2578' href='#n2578'>2578</a>
<a id='n2579' href='#n2579'>2579</a>
<a id='n2580' href='#n2580'>2580</a>
<a id='n2581' href='#n2581'>2581</a>
<a id='n2582' href='#n2582'>2582</a>
<a id='n2583' href='#n2583'>2583</a>
<a id='n2584' href='#n2584'>2584</a>
<a id='n2585' href='#n2585'>2585</a>
<a id='n2586' href='#n2586'>2586</a>
<a id='n2587' href='#n2587'>2587</a>
<a id='n2588' href='#n2588'>2588</a>
<a id='n2589' href='#n2589'>2589</a>
<a id='n2590' href='#n2590'>2590</a>
<a id='n2591' href='#n2591'>2591</a>
<a id='n2592' href='#n2592'>2592</a>
<a id='n2593' href='#n2593'>2593</a>
<a id='n2594' href='#n2594'>2594</a>
<a id='n2595' href='#n2595'>2595</a>
<a id='n2596' href='#n2596'>2596</a>
<a id='n2597' href='#n2597'>2597</a>
<a id='n2598' href='#n2598'>2598</a>
<a id='n2599' href='#n2599'>2599</a>
<a id='n2600' href='#n2600'>2600</a>
<a id='n2601' href='#n2601'>2601</a>
<a id='n2602' href='#n2602'>2602</a>
<a id='n2603' href='#n2603'>2603</a>
<a id='n2604' href='#n2604'>2604</a>
<a id='n2605' href='#n2605'>2605</a>
<a id='n2606' href='#n2606'>2606</a>
<a id='n2607' href='#n2607'>2607</a>
<a id='n2608' href='#n2608'>2608</a>
<a id='n2609' href='#n2609'>2609</a>
<a id='n2610' href='#n2610'>2610</a>
<a id='n2611' href='#n2611'>2611</a>
<a id='n2612' href='#n2612'>2612</a>
<a id='n2613' href='#n2613'>2613</a>
<a id='n2614' href='#n2614'>2614</a>
<a id='n2615' href='#n2615'>2615</a>
<a id='n2616' href='#n2616'>2616</a>
<a id='n2617' href='#n2617'>2617</a>
<a id='n2618' href='#n2618'>2618</a>
<a id='n2619' href='#n2619'>2619</a>
<a id='n2620' href='#n2620'>2620</a>
<a id='n2621' href='#n2621'>2621</a>
<a id='n2622' href='#n2622'>2622</a>
<a id='n2623' href='#n2623'>2623</a>
<a id='n2624' href='#n2624'>2624</a>
<a id='n2625' href='#n2625'>2625</a>
<a id='n2626' href='#n2626'>2626</a>
<a id='n2627' href='#n2627'>2627</a>
<a id='n2628' href='#n2628'>2628</a>
<a id='n2629' href='#n2629'>2629</a>
<a id='n2630' href='#n2630'>2630</a>
<a id='n2631' href='#n2631'>2631</a>
<a id='n2632' href='#n2632'>2632</a>
<a id='n2633' href='#n2633'>2633</a>
<a id='n2634' href='#n2634'>2634</a>
<a id='n2635' href='#n2635'>2635</a>
<a id='n2636' href='#n2636'>2636</a>
<a id='n2637' href='#n2637'>2637</a>
<a id='n2638' href='#n2638'>2638</a>
<a id='n2639' href='#n2639'>2639</a>
<a id='n2640' href='#n2640'>2640</a>
<a id='n2641' href='#n2641'>2641</a>
<a id='n2642' href='#n2642'>2642</a>
<a id='n2643' href='#n2643'>2643</a>
<a id='n2644' href='#n2644'>2644</a>
<a id='n2645' href='#n2645'>2645</a>
<a id='n2646' href='#n2646'>2646</a>
<a id='n2647' href='#n2647'>2647</a>
<a id='n2648' href='#n2648'>2648</a>
<a id='n2649' href='#n2649'>2649</a>
<a id='n2650' href='#n2650'>2650</a>
<a id='n2651' href='#n2651'>2651</a>
<a id='n2652' href='#n2652'>2652</a>
<a id='n2653' href='#n2653'>2653</a>
<a id='n2654' href='#n2654'>2654</a>
<a id='n2655' href='#n2655'>2655</a>
<a id='n2656' href='#n2656'>2656</a>
<a id='n2657' href='#n2657'>2657</a>
<a id='n2658' href='#n2658'>2658</a>
<a id='n2659' href='#n2659'>2659</a>
<a id='n2660' href='#n2660'>2660</a>
<a id='n2661' href='#n2661'>2661</a>
<a id='n2662' href='#n2662'>2662</a>
<a id='n2663' href='#n2663'>2663</a>
<a id='n2664' href='#n2664'>2664</a>
<a id='n2665' href='#n2665'>2665</a>
<a id='n2666' href='#n2666'>2666</a>
<a id='n2667' href='#n2667'>2667</a>
<a id='n2668' href='#n2668'>2668</a>
<a id='n2669' href='#n2669'>2669</a>
<a id='n2670' href='#n2670'>2670</a>
<a id='n2671' href='#n2671'>2671</a>
<a id='n2672' href='#n2672'>2672</a>
<a id='n2673' href='#n2673'>2673</a>
<a id='n2674' href='#n2674'>2674</a>
<a id='n2675' href='#n2675'>2675</a>
<a id='n2676' href='#n2676'>2676</a>
<a id='n2677' href='#n2677'>2677</a>
<a id='n2678' href='#n2678'>2678</a>
<a id='n2679' href='#n2679'>2679</a>
<a id='n2680' href='#n2680'>2680</a>
<a id='n2681' href='#n2681'>2681</a>
<a id='n2682' href='#n2682'>2682</a>
<a id='n2683' href='#n2683'>2683</a>
<a id='n2684' href='#n2684'>2684</a>
<a id='n2685' href='#n2685'>2685</a>
<a id='n2686' href='#n2686'>2686</a>
<a id='n2687' href='#n2687'>2687</a>
<a id='n2688' href='#n2688'>2688</a>
<a id='n2689' href='#n2689'>2689</a>
<a id='n2690' href='#n2690'>2690</a>
<a id='n2691' href='#n2691'>2691</a>
<a id='n2692' href='#n2692'>2692</a>
<a id='n2693' href='#n2693'>2693</a>
<a id='n2694' href='#n2694'>2694</a>
<a id='n2695' href='#n2695'>2695</a>
<a id='n2696' href='#n2696'>2696</a>
<a id='n2697' href='#n2697'>2697</a>
<a id='n2698' href='#n2698'>2698</a>
<a id='n2699' href='#n2699'>2699</a>
<a id='n2700' href='#n2700'>2700</a>
<a id='n2701' href='#n2701'>2701</a>
<a id='n2702' href='#n2702'>2702</a>
<a id='n2703' href='#n2703'>2703</a>
<a id='n2704' href='#n2704'>2704</a>
<a id='n2705' href='#n2705'>2705</a>
<a id='n2706' href='#n2706'>2706</a>
<a id='n2707' href='#n2707'>2707</a>
<a id='n2708' href='#n2708'>2708</a>
<a id='n2709' href='#n2709'>2709</a>
<a id='n2710' href='#n2710'>2710</a>
<a id='n2711' href='#n2711'>2711</a>
<a id='n2712' href='#n2712'>2712</a>
<a id='n2713' href='#n2713'>2713</a>
<a id='n2714' href='#n2714'>2714</a>
<a id='n2715' href='#n2715'>2715</a>
<a id='n2716' href='#n2716'>2716</a>
<a id='n2717' href='#n2717'>2717</a>
<a id='n2718' href='#n2718'>2718</a>
<a id='n2719' href='#n2719'>2719</a>
<a id='n2720' href='#n2720'>2720</a>
<a id='n2721' href='#n2721'>2721</a>
<a id='n2722' href='#n2722'>2722</a>
<a id='n2723' href='#n2723'>2723</a>
<a id='n2724' href='#n2724'>2724</a>
<a id='n2725' href='#n2725'>2725</a>
<a id='n2726' href='#n2726'>2726</a>
<a id='n2727' href='#n2727'>2727</a>
<a id='n2728' href='#n2728'>2728</a>
<a id='n2729' href='#n2729'>2729</a>
<a id='n2730' href='#n2730'>2730</a>
<a id='n2731' href='#n2731'>2731</a>
<a id='n2732' href='#n2732'>2732</a>
<a id='n2733' href='#n2733'>2733</a>
<a id='n2734' href='#n2734'>2734</a>
<a id='n2735' href='#n2735'>2735</a>
<a id='n2736' href='#n2736'>2736</a>
<a id='n2737' href='#n2737'>2737</a>
<a id='n2738' href='#n2738'>2738</a>
<a id='n2739' href='#n2739'>2739</a>
<a id='n2740' href='#n2740'>2740</a>
<a id='n2741' href='#n2741'>2741</a>
<a id='n2742' href='#n2742'>2742</a>
<a id='n2743' href='#n2743'>2743</a>
<a id='n2744' href='#n2744'>2744</a>
<a id='n2745' href='#n2745'>2745</a>
<a id='n2746' href='#n2746'>2746</a>
<a id='n2747' href='#n2747'>2747</a>
<a id='n2748' href='#n2748'>2748</a>
<a id='n2749' href='#n2749'>2749</a>
<a id='n2750' href='#n2750'>2750</a>
<a id='n2751' href='#n2751'>2751</a>
<a id='n2752' href='#n2752'>2752</a>
<a id='n2753' href='#n2753'>2753</a>
<a id='n2754' href='#n2754'>2754</a>
<a id='n2755' href='#n2755'>2755</a>
<a id='n2756' href='#n2756'>2756</a>
<a id='n2757' href='#n2757'>2757</a>
<a id='n2758' href='#n2758'>2758</a>
<a id='n2759' href='#n2759'>2759</a>
<a id='n2760' href='#n2760'>2760</a>
<a id='n2761' href='#n2761'>2761</a>
<a id='n2762' href='#n2762'>2762</a>
<a id='n2763' href='#n2763'>2763</a>
<a id='n2764' href='#n2764'>2764</a>
<a id='n2765' href='#n2765'>2765</a>
<a id='n2766' href='#n2766'>2766</a>
<a id='n2767' href='#n2767'>2767</a>
<a id='n2768' href='#n2768'>2768</a>
<a id='n2769' href='#n2769'>2769</a>
<a id='n2770' href='#n2770'>2770</a>
<a id='n2771' href='#n2771'>2771</a>
<a id='n2772' href='#n2772'>2772</a>
<a id='n2773' href='#n2773'>2773</a>
<a id='n2774' href='#n2774'>2774</a>
<a id='n2775' href='#n2775'>2775</a>
<a id='n2776' href='#n2776'>2776</a>
<a id='n2777' href='#n2777'>2777</a>
<a id='n2778' href='#n2778'>2778</a>
<a id='n2779' href='#n2779'>2779</a>
<a id='n2780' href='#n2780'>2780</a>
<a id='n2781' href='#n2781'>2781</a>
<a id='n2782' href='#n2782'>2782</a>
<a id='n2783' href='#n2783'>2783</a>
<a id='n2784' href='#n2784'>2784</a>
<a id='n2785' href='#n2785'>2785</a>
<a id='n2786' href='#n2786'>2786</a>
<a id='n2787' href='#n2787'>2787</a>
<a id='n2788' href='#n2788'>2788</a>
<a id='n2789' href='#n2789'>2789</a>
<a id='n2790' href='#n2790'>2790</a>
<a id='n2791' href='#n2791'>2791</a>
<a id='n2792' href='#n2792'>2792</a>
<a id='n2793' href='#n2793'>2793</a>
<a id='n2794' href='#n2794'>2794</a>
<a id='n2795' href='#n2795'>2795</a>
<a id='n2796' href='#n2796'>2796</a>
<a id='n2797' href='#n2797'>2797</a>
<a id='n2798' href='#n2798'>2798</a>
<a id='n2799' href='#n2799'>2799</a>
<a id='n2800' href='#n2800'>2800</a>
<a id='n2801' href='#n2801'>2801</a>
<a id='n2802' href='#n2802'>2802</a>
<a id='n2803' href='#n2803'>2803</a>
<a id='n2804' href='#n2804'>2804</a>
<a id='n2805' href='#n2805'>2805</a>
<a id='n2806' href='#n2806'>2806</a>
<a id='n2807' href='#n2807'>2807</a>
<a id='n2808' href='#n2808'>2808</a>
<a id='n2809' href='#n2809'>2809</a>
<a id='n2810' href='#n2810'>2810</a>
<a id='n2811' href='#n2811'>2811</a>
<a id='n2812' href='#n2812'>2812</a>
<a id='n2813' href='#n2813'>2813</a>
<a id='n2814' href='#n2814'>2814</a>
<a id='n2815' href='#n2815'>2815</a>
<a id='n2816' href='#n2816'>2816</a>
<a id='n2817' href='#n2817'>2817</a>
<a id='n2818' href='#n2818'>2818</a>
<a id='n2819' href='#n2819'>2819</a>
<a id='n2820' href='#n2820'>2820</a>
<a id='n2821' href='#n2821'>2821</a>
<a id='n2822' href='#n2822'>2822</a>
<a id='n2823' href='#n2823'>2823</a>
<a id='n2824' href='#n2824'>2824</a>
<a id='n2825' href='#n2825'>2825</a>
<a id='n2826' href='#n2826'>2826</a>
<a id='n2827' href='#n2827'>2827</a>
<a id='n2828' href='#n2828'>2828</a>
<a id='n2829' href='#n2829'>2829</a>
<a id='n2830' href='#n2830'>2830</a>
<a id='n2831' href='#n2831'>2831</a>
<a id='n2832' href='#n2832'>2832</a>
<a id='n2833' href='#n2833'>2833</a>
<a id='n2834' href='#n2834'>2834</a>
<a id='n2835' href='#n2835'>2835</a>
<a id='n2836' href='#n2836'>2836</a>
<a id='n2837' href='#n2837'>2837</a>
<a id='n2838' href='#n2838'>2838</a>
<a id='n2839' href='#n2839'>2839</a>
<a id='n2840' href='#n2840'>2840</a>
<a id='n2841' href='#n2841'>2841</a>
<a id='n2842' href='#n2842'>2842</a>
<a id='n2843' href='#n2843'>2843</a>
<a id='n2844' href='#n2844'>2844</a>
<a id='n2845' href='#n2845'>2845</a>
<a id='n2846' href='#n2846'>2846</a>
<a id='n2847' href='#n2847'>2847</a>
<a id='n2848' href='#n2848'>2848</a>
<a id='n2849' href='#n2849'>2849</a>
<a id='n2850' href='#n2850'>2850</a>
<a id='n2851' href='#n2851'>2851</a>
<a id='n2852' href='#n2852'>2852</a>
<a id='n2853' href='#n2853'>2853</a>
<a id='n2854' href='#n2854'>2854</a>
<a id='n2855' href='#n2855'>2855</a>
<a id='n2856' href='#n2856'>2856</a>
<a id='n2857' href='#n2857'>2857</a>
<a id='n2858' href='#n2858'>2858</a>
<a id='n2859' href='#n2859'>2859</a>
<a id='n2860' href='#n2860'>2860</a>
<a id='n2861' href='#n2861'>2861</a>
<a id='n2862' href='#n2862'>2862</a>
<a id='n2863' href='#n2863'>2863</a>
<a id='n2864' href='#n2864'>2864</a>
<a id='n2865' href='#n2865'>2865</a>
<a id='n2866' href='#n2866'>2866</a>
<a id='n2867' href='#n2867'>2867</a>
<a id='n2868' href='#n2868'>2868</a>
<a id='n2869' href='#n2869'>2869</a>
<a id='n2870' href='#n2870'>2870</a>
<a id='n2871' href='#n2871'>2871</a>
<a id='n2872' href='#n2872'>2872</a>
<a id='n2873' href='#n2873'>2873</a>
<a id='n2874' href='#n2874'>2874</a>
<a id='n2875' href='#n2875'>2875</a>
<a id='n2876' href='#n2876'>2876</a>
<a id='n2877' href='#n2877'>2877</a>
<a id='n2878' href='#n2878'>2878</a>
<a id='n2879' href='#n2879'>2879</a>
<a id='n2880' href='#n2880'>2880</a>
<a id='n2881' href='#n2881'>2881</a>
<a id='n2882' href='#n2882'>2882</a>
<a id='n2883' href='#n2883'>2883</a>
<a id='n2884' href='#n2884'>2884</a>
<a id='n2885' href='#n2885'>2885</a>
<a id='n2886' href='#n2886'>2886</a>
<a id='n2887' href='#n2887'>2887</a>
<a id='n2888' href='#n2888'>2888</a>
<a id='n2889' href='#n2889'>2889</a>
<a id='n2890' href='#n2890'>2890</a>
<a id='n2891' href='#n2891'>2891</a>
<a id='n2892' href='#n2892'>2892</a>
<a id='n2893' href='#n2893'>2893</a>
<a id='n2894' href='#n2894'>2894</a>
<a id='n2895' href='#n2895'>2895</a>
<a id='n2896' href='#n2896'>2896</a>
<a id='n2897' href='#n2897'>2897</a>
<a id='n2898' href='#n2898'>2898</a>
<a id='n2899' href='#n2899'>2899</a>
<a id='n2900' href='#n2900'>2900</a>
<a id='n2901' href='#n2901'>2901</a>
<a id='n2902' href='#n2902'>2902</a>
<a id='n2903' href='#n2903'>2903</a>
<a id='n2904' href='#n2904'>2904</a>
<a id='n2905' href='#n2905'>2905</a>
<a id='n2906' href='#n2906'>2906</a>
<a id='n2907' href='#n2907'>2907</a>
<a id='n2908' href='#n2908'>2908</a>
<a id='n2909' href='#n2909'>2909</a>
<a id='n2910' href='#n2910'>2910</a>
<a id='n2911' href='#n2911'>2911</a>
<a id='n2912' href='#n2912'>2912</a>
<a id='n2913' href='#n2913'>2913</a>
<a id='n2914' href='#n2914'>2914</a>
<a id='n2915' href='#n2915'>2915</a>
<a id='n2916' href='#n2916'>2916</a>
<a id='n2917' href='#n2917'>2917</a>
<a id='n2918' href='#n2918'>2918</a>
<a id='n2919' href='#n2919'>2919</a>
<a id='n2920' href='#n2920'>2920</a>
<a id='n2921' href='#n2921'>2921</a>
<a id='n2922' href='#n2922'>2922</a>
<a id='n2923' href='#n2923'>2923</a>
<a id='n2924' href='#n2924'>2924</a>
<a id='n2925' href='#n2925'>2925</a>
<a id='n2926' href='#n2926'>2926</a>
<a id='n2927' href='#n2927'>2927</a>
<a id='n2928' href='#n2928'>2928</a>
<a id='n2929' href='#n2929'>2929</a>
<a id='n2930' href='#n2930'>2930</a>
<a id='n2931' href='#n2931'>2931</a>
<a id='n2932' href='#n2932'>2932</a>
<a id='n2933' href='#n2933'>2933</a>
<a id='n2934' href='#n2934'>2934</a>
<a id='n2935' href='#n2935'>2935</a>
<a id='n2936' href='#n2936'>2936</a>
<a id='n2937' href='#n2937'>2937</a>
<a id='n2938' href='#n2938'>2938</a>
<a id='n2939' href='#n2939'>2939</a>
<a id='n2940' href='#n2940'>2940</a>
<a id='n2941' href='#n2941'>2941</a>
<a id='n2942' href='#n2942'>2942</a>
<a id='n2943' href='#n2943'>2943</a>
<a id='n2944' href='#n2944'>2944</a>
<a id='n2945' href='#n2945'>2945</a>
<a id='n2946' href='#n2946'>2946</a>
<a id='n2947' href='#n2947'>2947</a>
<a id='n2948' href='#n2948'>2948</a>
<a id='n2949' href='#n2949'>2949</a>
<a id='n2950' href='#n2950'>2950</a>
<a id='n2951' href='#n2951'>2951</a>
<a id='n2952' href='#n2952'>2952</a>
<a id='n2953' href='#n2953'>2953</a>
<a id='n2954' href='#n2954'>2954</a>
<a id='n2955' href='#n2955'>2955</a>
<a id='n2956' href='#n2956'>2956</a>
<a id='n2957' href='#n2957'>2957</a>
<a id='n2958' href='#n2958'>2958</a>
<a id='n2959' href='#n2959'>2959</a>
<a id='n2960' href='#n2960'>2960</a>
<a id='n2961' href='#n2961'>2961</a>
<a id='n2962' href='#n2962'>2962</a>
<a id='n2963' href='#n2963'>2963</a>
<a id='n2964' href='#n2964'>2964</a>
<a id='n2965' href='#n2965'>2965</a>
<a id='n2966' href='#n2966'>2966</a>
<a id='n2967' href='#n2967'>2967</a>
<a id='n2968' href='#n2968'>2968</a>
<a id='n2969' href='#n2969'>2969</a>
<a id='n2970' href='#n2970'>2970</a>
<a id='n2971' href='#n2971'>2971</a>
<a id='n2972' href='#n2972'>2972</a>
<a id='n2973' href='#n2973'>2973</a>
<a id='n2974' href='#n2974'>2974</a>
<a id='n2975' href='#n2975'>2975</a>
<a id='n2976' href='#n2976'>2976</a>
<a id='n2977' href='#n2977'>2977</a>
<a id='n2978' href='#n2978'>2978</a>
<a id='n2979' href='#n2979'>2979</a>
<a id='n2980' href='#n2980'>2980</a>
<a id='n2981' href='#n2981'>2981</a>
<a id='n2982' href='#n2982'>2982</a>
<a id='n2983' href='#n2983'>2983</a>
<a id='n2984' href='#n2984'>2984</a>
<a id='n2985' href='#n2985'>2985</a>
<a id='n2986' href='#n2986'>2986</a>
<a id='n2987' href='#n2987'>2987</a>
<a id='n2988' href='#n2988'>2988</a>
<a id='n2989' href='#n2989'>2989</a>
<a id='n2990' href='#n2990'>2990</a>
<a id='n2991' href='#n2991'>2991</a>
<a id='n2992' href='#n2992'>2992</a>
<a id='n2993' href='#n2993'>2993</a>
<a id='n2994' href='#n2994'>2994</a>
<a id='n2995' href='#n2995'>2995</a>
<a id='n2996' href='#n2996'>2996</a>
<a id='n2997' href='#n2997'>2997</a>
<a id='n2998' href='#n2998'>2998</a>
<a id='n2999' href='#n2999'>2999</a>
<a id='n3000' href='#n3000'>3000</a>
<a id='n3001' href='#n3001'>3001</a>
<a id='n3002' href='#n3002'>3002</a>
<a id='n3003' href='#n3003'>3003</a>
<a id='n3004' href='#n3004'>3004</a>
<a id='n3005' href='#n3005'>3005</a>
</pre></td>
<td class='lines'><pre><code>