proc helpC100 {} {
puts "List of useful functions for C100 processor:"
puts "1) reset init: will set up your Telo board"
puts "2) setupNOR: will setup NOR access"
puts "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
puts "4) setupGPIO: will setup GPIOs for Telo board"
puts "5) showGPIO: will show current GPIO config registers"
puts "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
puts "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
puts "8) showAmbaClk: will show current config registers for Amba Bus Clock"
puts "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
puts "10) showArmClk: will show current config registers for Arm Bus Clock"
puts "11) setupArmClk: will setup Amba Bus Clock=450MHz"
puts "12) ooma_board_detect: will show which version of Telo you have"
puts "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
puts "14) showDDR2: will show DDR2 config registers"
puts "15) showWatchdog: will show current regster config for watchdog"
puts "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
puts "17) bootNOR: will boot Telo from NOR"
puts "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
puts "19) putcUART0: will print a character on UART0"
puts "20) putsUART0: will print a string on UART0"
puts "21) trainDDR2: will run DDR2 training program"
puts "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
}
# mrw,mmw from davinci.cfg
# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
set value ""
ocd_mem2array value 32 $reg 1
return $value(0)
}
# read a 64-bit register (memory mapped)
proc mr64bit {reg} {
set value ""
ocd_mem2array value 32 $reg 2
return $value
}
# write a 64-bit register (memory mapped)
proc mw64bit {reg value} {
set high [expr $value >> 32]
set low [expr $value & 0xffffffff]
#puts [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
mww $reg $low
mww [expr $reg+4] $high
}
# mmw: "memory modify word", updates value of $reg
# $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
set old [mrw $reg]
set new [expr ($old & ~$clearbits) | $setbits]
mww $reg $new
}
proc showNOR {} {
puts "This is the current NOR setup"
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
set EX_MFSM_REG [regs EX_MFSM_REG ]
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
puts [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
puts [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
puts [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
puts [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
puts [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
puts [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
puts [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
puts [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
puts [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
}
proc showGPIO {} {
puts "This is the current GPIO register setup"
# GPIO outputs register
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# GPIO Output Enable register
set GPIO_OE_REG [regs GPIO_OE_REG]
set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
# GPIO input register
set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set MUX_CONF_REG [regs MUX_CONF_REG]
set SYSCONF_REG [regs SYSCONF_REG]
set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
puts [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
puts [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
puts [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
puts [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
puts [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
puts [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
puts [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
puts [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
puts [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
puts [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
proc showAmbaClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
puts [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
puts [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
puts [format "w: %d" $w]
puts [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
}
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
proc setupAmbaClk {} {
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
set w [config w_amba]
set x [config x_amba]
set y [config y_amba]
puts [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
#puts [format "setupAmbaClk: w= %d" $w]
#puts [format "setupAmbaClk: x= %d" $x]
#puts [format "setupAmbaClk: y= %d" $y]
# set PLL into BYPASS mode using MUX
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
# do an internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
# openocd smallest resolution is 1ms so, wait 1ms
sleep 1
# disable the PLL
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
# wait 1ms
sleep 1
# enable the PLL
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
sleep 1
# set X, W and X
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
puts "Wating for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
proc showArmClk {} {
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
puts [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
puts [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
puts [format "w: %d" $w]
puts [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
}
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
# Arm Clock is used by two ARM1136 cores
proc setupArmClk {} {
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
set ARM_AHB_BYP [regs ARM_AHB_BYP]
set PLL_DISABLE [regs PLL_DISABLE]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
set DIV_BYPASS [regs DIV_BYPASS]
set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
set w [config w_arm]
set x [config x_arm]
set y [config y_arm]
puts [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
#puts [format "setupArmClk: w= %d" $w]
#puts [format "setupArmaClk: x= %d" $x]
#puts [format "setupArmaClk: y= %d" $y]
# set PLL into BYPASS mode using MUX
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
# do an internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
# openocd smallest resolution is 1ms so, wait 1ms
sleep 1
# disable the PLL
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
# wait 1ms
sleep 1
# enable the PLL
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
sleep 1
# set X, W and X
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
puts "Wating for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
}
proc setupPLL {} {
puts "PLLs setup"
setupAmbaClk
setupArmClk
}
# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
proc setupDDR2 {} {
puts "Configuring DDR2"
set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
set MEMORY_CR [regs MEMORY_CR]
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
set DDR_RST [regs DDR_RST]
# put DDR controller in reset (so that it is reset and correctly configured)
# this is only necessary if DDR was previously confiured
# and not reset.
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
set M [expr 1024 * 1024]
set DDR_SZ_1024M [expr 1024 * $M]
set DDR_SZ_256M [expr 256 * $M]
set DDR_SZ_128M [expr 128 * $M]
set DDR_SZ_64M [expr 64 * $M]
# ooma_board_detect returns DDR2 memory size
set tmp [ooma_board_detect]
if {$tmp == "128M"} {
puts "DDR2 size 128MB"
set ddr_size $DDR_SZ_128M
} elseif {$tmp == "256M"} {
puts "DDR2 size 256MB"
set ddr_size $DDR_SZ_256M
} else {
puts "Don't know how to handle this DDR2 size?"
}
# Memory setup register
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
# disbale ROM remap
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
mmw $BLOCK_RESET_REG $DDR_RST 0x0
# min. 20 ops delay
sleep 1
# This will setup Denali DDR2 controller
if {$tmp == "128M"} {
configureDDR2regs_128M
} elseif {$tmp == "256M"} {
configureDDR2regs_256B
} else {
puts "Don't know how to configure DDR2 setup?"
}
}
proc showDDR2 {} {
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
set tmp [mr64bit $DENALI_CTL_00_DATA]
puts [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_01_DATA]
puts [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_02_DATA]
puts [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_03_DATA]
puts [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_04_DATA]
puts [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_05_DATA]
puts [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_06_DATA]
puts [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_07_DATA]
puts [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_08_DATA]
puts [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_09_DATA]
puts [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_10_DATA]
puts [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_11_DATA]
puts [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_12_DATA]
puts [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_13_DATA]
puts [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_14_DATA]
puts [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_15_DATA]
puts [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_16_DATA]
puts [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_17_DATA]
puts [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_18_DATA]
puts [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_19_DATA]
puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
set tmp [mr64bit $DENALI_CTL_20_DATA]
puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
}
proc initC100 {} {
# this follows u-boot/cpu/arm1136/start.S
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
# enable address lines A15-A21
mmw $GPIO_IOCTRL_REG 0xf 0x0
# set ARM into supervisor mode (SVC32)
# disable IRQ, FIQ
# Do I need this in JTAG mode?
# it really should be done as 'and ~0x1f | 0xd3 but
# openocd does not support this yet
reg cpsr 0xd3
# /*
# * flush v4 I/D caches
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr 15 0 7 7 0 0x0
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mcr 15 0 8 7 0 0x0
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
mrc 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
mcr 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
mww [expr $APB_ACCESS_WS_REG] 0x40
# AHB init
# // enable all 6 masters for ARAM
mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
# // enable all 6 masters for EBUS
mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
# ARAM init
# // disable pipeline mode in ARAM
# I don't think this is documented anywhere?
mww $INTC_ARM1_CONTROL_REG 0x1
# configure clocks
setupPLL
# enable cache
# ? (u-boot does nothing here)
# DDR2 memory init
setupDDR2
setupUART0
putsUART0 "C100 initialization complete.\n"
puts "C100 initialization complete."
}
# show current state of watchdog timer
proc showWatchdog {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
}
# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
# this will trigger watchdog reset
# the sw. reset does not work on C100
# watchdog reset effectively works as hw. reset
proc reboot {} {
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
# this is because regsiter writes are slow over JTAG and
# I don't want to miss the high_bound==curr_count condition
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
puts "JTAG speed lowered to 100kHz"
jtag_khz 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
# puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# sleep 1
#
#}
while {[c100.cpu curstate] != "running"} { sleep 1}
puts "done."
puts [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
}
a id='n574' href='#n574'>574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
|