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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:16:08 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-08-26 19:16:08 +0000 |
| commit | 56b346447bb9799640ef328d4d867168be813119 (patch) | |
| tree | 89c5d8b7f182d59c09784408ef20349cc2cbcd50 | |
| parent | dce1cdc9fb24ddef693a6ff158d3b901f6f9e78b (diff) | |
| download | openocd_libswd-56b346447bb9799640ef328d4d867168be813119.tar.gz openocd_libswd-56b346447bb9799640ef328d4d867168be813119.tar.bz2 openocd_libswd-56b346447bb9799640ef328d4d867168be813119.tar.xz openocd_libswd-56b346447bb9799640ef328d4d867168be813119.zip | |
Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before executing a new instruction wait for the previous
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
| -rw-r--r-- | src/target/cortex_a8.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 84ace67d..dcf246fa 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -161,7 +161,15 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) swjdp_common_t *swjdp = &armv7a->swjdp_info; LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); + do + { + retvalue = mem_ap_read_atomic_u32(swjdp, + OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + } + while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */ + mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode); + do { retvalue = mem_ap_read_atomic_u32(swjdp, |