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author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 08:22:02 +0000 |
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committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-04 08:22:02 +0000 |
commit | 81b57a3fb615e107e0e6b5e99f7fe0a72a977d50 (patch) | |
tree | 0db0913443111eff49c5228d64896f639a48a2ec | |
parent | ee329275d373567ca52f4116569aac24d059ea43 (diff) | |
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Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
-rw-r--r-- | src/target/cortex_a8.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index a806669d..6ef585cc 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -430,6 +430,13 @@ int cortex_a8_halt(target_t *target) retval = mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1); + /* + * enter halting debug mode + */ + mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + retval = mem_ap_write_atomic_u32(swjdp, + OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE)); + if (retval != ERROR_OK) goto out; |