diff options
| author | mifi <mifi@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-02-06 19:25:42 +0000 |
|---|---|---|
| committer | mifi <mifi@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-02-06 19:25:42 +0000 |
| commit | a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f (patch) | |
| tree | a0b039ac2d46b2dc1777310be6b9086468483e5c /src/target/cortex_m3.c | |
| parent | 4d88f024a614f699d5ce5673520762bcfdf96ce2 (diff) | |
| download | openocd_libswd-a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f.tar.gz openocd_libswd-a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f.tar.bz2 openocd_libswd-a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f.tar.xz openocd_libswd-a34e4b39c47cd9f67f3f70be36c1b2f25ab23f5f.zip | |
- added patch to solve problem with AT91SAM9260 (dirty register)
(thanks to Øyvind Harboe for the patch)
git-svn-id: svn://svn.berlios.de/openocd/trunk@282 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/cortex_m3.c')
| -rw-r--r-- | src/target/cortex_m3.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 279d986a..db9dd054 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -137,7 +137,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval ahbap_write_system_u32(swjdp, 0x20000000, opcode); ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; @@ -320,7 +320,7 @@ int cortex_m3_debug_entry(target_t *target) /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/ if (xPSR & 0xf00) { - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid; cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } @@ -1149,8 +1149,8 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_read_coreregister_u32(swjdp, value, 0); - armv7m->core_cache->reg_list[0].dirty = 1; - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); DEBUG("load from special reg %i value 0x%x", SYSm, *value); @@ -1175,7 +1175,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty if (retval != ERROR_OK) { ERROR("JTAG failure %i", retval); - armv7m->core_cache->reg_list[num].dirty = 1; + armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } DEBUG("write core reg %i value 0x%x", num, value); @@ -1195,7 +1195,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_write_coreregister_u32(swjdp, tempr0, 0); - armv7m->core_cache->reg_list[15].dirty = 1; + armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); DEBUG("write special reg %i value 0x%x ", SYSm, value); |