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| author | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-18 23:01:16 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-07-19 08:36:14 +0200 |
| commit | 19fc52f00869a4c607483d96c459a51f3979c8db (patch) | |
| tree | 073a0acc5117b4fe71cbd88b0ed4a817040278c4 /src/target | |
| parent | d10f0def80f8837398b9176388ed6110fcebfd2d (diff) | |
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cortex a8: add missing error handling for mem_ap_read_atomic_u32()
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/cortex_a8.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 90e1a00f..82ce9a18 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -11,6 +11,9 @@ * Copyright (C) 2009 by Dirk Behme * * dirk.behme@gmail.com - copy from cortex_m3 * * * + * Copyright (C) 2010 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -228,6 +231,8 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, { retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; } retval = mem_ap_read_atomic_u32(swjdp, @@ -251,6 +256,8 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Check that DCCRX is not full */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); @@ -352,10 +359,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + return retval; } retval = mem_ap_read_atomic_u32(swjdp, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); + if (retval != ERROR_OK) + return retval; //LOG_DEBUG("read DCC 0x%08" PRIx32, *data); if (dscr_p) |