- add missing svn props from previous commit

git-svn-id: svn://svn.berlios.de/openocd/trunk@1395 b42882b7-edfa-0310-969c-e2dbd0fdcd60

4 files changed, 174 insertions, 174 deletions

diff --git a/src/target/board/sheevaplug.cfg b/src/target/board/sheevaplug.cfg
index 2dd2cae5..e9c68328 100644
--- a/src/target/board/sheevaplug.cfg
+++ b/src/target/board/sheevaplug.cfg
@@ -1,111 +1,111 @@
-# Marvell SheevaPlug 

-

-source [find interface/sheevaplug.cfg]

-source [find target/feroceon.cfg]

-

-$_TARGETNAME configure -event reset-init { sheevaplug_init }

-

-$_TARGETNAME configure \

-	-work-area-phys 0x10000000 \

-	-work-area-size 65536 \

-	-work-area-backup 0

-

-arm7_9 dcc_downloads enable

-

-# this assumes the hardware default peripherals location before u-Boot moves it

-nand device orion 0 0xd8000000

-

-proc sheevaplug_init { } {

-

-	arm926ejs cp15 0 0 1 0 0x00052078

-

-	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register

-	mww 0xD0001404 0x39543000 #  Dunit Control Low Register

-	mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register

-	mww 0xD000140C 0x00000833 #  DDR SDRAM Timing (High) Register

-	mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register

-	mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register

-	mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register

-	mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register

-	mww 0xD0001420 0x00000042 #  DDR SDRAM Extended Mode Register

-	mww 0xD0001424 0x0000F17F #  Dunit Control High Register

-	mww 0xD0001428 0x00085520 #  Dunit Control High Register

-	mww 0xD000147c 0x00008552 #  Dunit Control High Register

-	mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register

-	mww 0xD0001508 0x10000000 #  CS1n Base Register

-	mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register

-	mww 0xD0001514 0x00000000 #  CS2n Size Register

-	mww 0xD000151C 0x00000000 #  CS3n Size Register

-	mww 0xD0001494 0x003C0000 #  DDR2 SDRAM ODT Control (Low) Register

-	mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister

-	mww 0xD000149C 0x0000F80F #  DDR2 Dunit ODT Control Register

-	mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register

-	mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-	mww 0xD0020204 0x00000000 #              "

-

-	mww 0xD0010000 0x01111111 #  MPP  0 to 7

-	mww 0xD0010004 0x11113322 #  MPP  8 to 15

-	mww 0xD0010008 0x00001111 #  MPP 16 to 23

-

-	mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister

-	mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register

-	mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register

-

-}

-

-proc sheevaplug_reflash_uboot { } {

-

-	# reflash the u-Boot binary

-	#reset init

-	nand probe 0

-	nand erase 0 0 4

-	nand write 0 uboot.bin 0

-	reset run

-

-}

-

-proc sheevaplug_load_uboot { } {

-

-	# load u-Boot into RAM

-	#reset init

-	load_image /tmp/uboot.elf

-	verify_image uboot.elf

-	resume 0x00600000

-

-}

-

+# Marvell SheevaPlug 
+
+source [find interface/sheevaplug.cfg]
+source [find target/feroceon.cfg]
+
+$_TARGETNAME configure -event reset-init { sheevaplug_init }
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+nand device orion 0 0xd8000000
+
+proc sheevaplug_init { } {
+
+	arm926ejs cp15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x39543000 #  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000833 #  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000042 #  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F #  Dunit Control High Register
+	mww 0xD0001428 0x00085520 #  Dunit Control High Register
+	mww 0xD000147c 0x00008552 #  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register
+	mww 0xD0001508 0x10000000 #  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register
+	mww 0xD0001514 0x00000000 #  CS2n Size Register
+	mww 0xD000151C 0x00000000 #  CS3n Size Register
+	mww 0xD0001494 0x003C0000 #  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000F80F #  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+
+	mww 0xD0010000 0x01111111 #  MPP  0 to 7
+	mww 0xD0010004 0x11113322 #  MPP  8 to 15
+	mww 0xD0010008 0x00001111 #  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register
+
+}
+
+proc sheevaplug_reflash_uboot { } {
+
+	# reflash the u-Boot binary
+	#reset init
+	nand probe 0
+	nand erase 0 0 4
+	nand write 0 uboot.bin 0
+	reset run
+
+}
+
+proc sheevaplug_load_uboot { } {
+
+	# load u-Boot into RAM
+	#reset init
+	load_image /tmp/uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
+
diff --git a/src/target/interface/sheevaplug.cfg b/src/target/interface/sheevaplug.cfg
index e7e72a98..64d52b25 100644
--- a/src/target/interface/sheevaplug.cfg
+++ b/src/target/interface/sheevaplug.cfg
@@ -1,4 +1,4 @@
-interface ft2232

-ft2232_layout sheevaplug

-ft2232_vid_pid 0x0403 0x6010

-jtag_khz 3000

+interface ft2232
+ft2232_layout sheevaplug
+ft2232_vid_pid 0x0403 0x6010
+jtag_khz 3000
diff --git a/src/target/target/feroceon.cfg b/src/target/target/feroceon.cfg
index 26f63f2f..552831a8 100644
--- a/src/target/target/feroceon.cfg
+++ b/src/target/target/feroceon.cfg
@@ -1,30 +1,30 @@
-######################################

-# Target:    Marvell Feroceon CPU core

-######################################

-

-if { [info exists CHIPNAME] } {	

-   set  _CHIPNAME $CHIPNAME    

-} else {	 

-   set  _CHIPNAME feroceon

-}

-

-if { [info exists ENDIAN] } {	

-   set  _ENDIAN $ENDIAN    

-} else {	 

-   set  _ENDIAN little

-}

-

-if { [info exists CPUTAPID ] } {

-   set _CPUTAPID $CPUTAPID

-} else {

-   set _CPUTAPID 0x20a023d3

-}

-

-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]

-target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME

-

-reset_config trst_and_srst

-jtag_nsrst_delay 200

-jtag_ntrst_delay 200

-

+######################################
+# Target:    Marvell Feroceon CPU core
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME feroceon
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x20a023d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
diff --git a/src/target/test/syntax1.cfg b/src/target/test/syntax1.cfg
index c312f606..fb88d5ae 100644
--- a/src/target/test/syntax1.cfg
+++ b/src/target/test/syntax1.cfg
@@ -1,29 +1,29 @@
-jtag_nsrst_delay 200

-jtag_ntrst_delay 200

-

-#use combined on interfaces or targets that can't set TRST/SRST separately

-reset_config trst_and_srst srst_pulls_trst

-

-#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough

-jtag_reset 1 1

-jtag_reset 0 0

-

-#jtag scan chain

-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)

-jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f

-

-#target configuration

-#daemon_startup reset

-

-set _TARGETNAME [format "%s.cpu" lpc2148]

-target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0

-

-$_TARGETNAME configure -event reset-init { 

-soft_reset_halt 

-mvb 0xE01FC040 0x01 

-}

-

-

-

-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765

-

+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
+jtag_reset 1 1
+jtag_reset 0 0
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
+
+#target configuration
+#daemon_startup reset
+
+set _TARGETNAME [format "%s.cpu" lpc2148]
+target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init { 
+soft_reset_halt 
+mvb 0xE01FC040 0x01 
+}
+
+
+
+flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
+