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authorLuca Ellero <lroluk@gmail.com>2011-04-13 18:55:18 +0000
committerØyvind Harboe <oyvind.harboe@zylin.com>2011-04-13 21:32:24 +0200
commit81f238f522ecba6c24217d94b17086e2d4fcce59 (patch)
tree171d77d3e6937c6a343c9361de93e55526443161 /src
parent041953f3b1e615ed898068a659d429e20f7a4007 (diff)
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Add opcodes for load/store registers words immediate post-indexed
Signed-off-by: Luca Ellero <lroluk@gmail.com>
Diffstat (limited to 'src')
-rwxr-xr-x[-rw-r--r--]src/target/arm_opcodes.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index b77721e6..9a48e6d0 100644..100755
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -86,6 +86,12 @@
#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+/* Load Register Word Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
+
/* Load Register Halfword Immediate Post-Index
* Rd: register to load
* Rn: base register
@@ -98,6 +104,12 @@
*/
#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
+/* Store register Word Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
+
/* Store register Halfword Immediate Post-Index
* Rd: register to store
* Rn: base register