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authordbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-21 18:48:22 +0000
committerdbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-21 18:48:22 +0000
commit71af49ca7fb11b0bd0c1ba9578826f49288b68ef (patch)
tree9ba8dd705f83aa44879bc7b5817ce40317f1fc28 /tcl/board/at91sam9g20-ek.cfg
parent86a7d813a165fda2816b8152342219b6c4ae2fc4 (diff)
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Remove annoying end-of-line whitespace from tcl/* files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/board/at91sam9g20-ek.cfg')
-rw-r--r--tcl/board/at91sam9g20-ek.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index c9deb144..00ab7faf 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -62,7 +62,7 @@ proc read_register {register} {
}
proc at91sam9g20_init { } {
-
+
# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
# recommended procedure outlined in the AT91SAM9G20 technical manual.
@@ -94,7 +94,7 @@ proc at91sam9g20_init { } {
mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
+
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.