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authorAntonio Borneo <borneo.antonio@gmail.com>2010-12-19 01:22:53 +0800
committerØyvind Harboe <oyvind.harboe@zylin.com>2010-12-18 21:04:22 +0100
commit30da7c67cec8b315972377b5389735ff11f6042c (patch)
treef5735bd53edf0b43ef27c5058fdab817d2034462 /tcl/board/hitex_lpc2929.cfg
parentaf3f77a1777e4f28ec1a14122f4800ca3467e4c7 (diff)
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TCL: fix non TCL comments
End of line comments fixed with ';' before '#'. Added few additional 'space' to keep indentation in multi-line comments. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/board/hitex_lpc2929.cfg')
-rw-r--r--tcl/board/hitex_lpc2929.cfg120
1 files changed, 60 insertions, 60 deletions
diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index 13d38729..d2515371 100644
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -34,73 +34,73 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
$_TARGETNAME configure -event reset-init {
# Flash
- mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached
+ mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
# Use PLL
- mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz
- mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal
- mww 0xFFFF8028 0x00000005 # PLL: (power down)
- mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up)
- # --> f=112 MHz, fcco=224 MHz
+ mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
+ mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal
+ mww 0xFFFF8028 0x00000005 ;# PLL: (power down)
+ mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up)
+ # --> f=112 MHz, fcco=224 MHz
sleep 100
- mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
+ mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
adapter_khz 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
- mww 0xE0001138 0x0000001F # P1.14 = D0
- mww 0xE000113C 0x0000001F # P1.15 = D1
- mww 0xE0001140 0x0000001F # P1.16 = D2
- mww 0xE0001144 0x0000001F # P1.17 = D3
- mww 0xE0001148 0x0000001F # P1.18 = D4
- mww 0xE000114C 0x0000001F # P1.19 = D5
- mww 0xE0001150 0x0000001F # P1.20 = D6
- mww 0xE0001154 0x0000001F # P1.21 = D7
- mww 0xE0001200 0x0000001F # P2.0 = D8
- mww 0xE0001204 0x0000001F # P2.1 = D9
- mww 0xE0001208 0x0000001F # P2.2 = D10
- mww 0xE000120C 0x0000001F # P2.3 = D11
- mww 0xE0001210 0x0000001F # P2.4 = D12
- mww 0xE0001214 0x0000001F # P2.5 = D13
- mww 0xE0001218 0x0000001F # P2.6 = D14
- mww 0xE000121C 0x0000001F # P2.7 = D15
- mww 0xE0001104 0x00000007 # P1.1 = A1
- mww 0xE0001108 0x00000007 # P1.2 = A2
- mww 0xE000110C 0x00000007 # P1.3 = A3
- mww 0xE0001110 0x00000007 # P1.4 = A4
- mww 0xE0001114 0x00000007 # P1.5 = A5
- mww 0xE0001118 0x00000007 # P1.6 = A6
- mww 0xE000111C 0x00000007 # P1.7 = A7
- mww 0xE0001028 0x00000007 # P0.10 = A8
- mww 0xE000102C 0x00000007 # P0.11 = A9
- mww 0xE0001030 0x00000007 # P0.12 = A10
- mww 0xE0001034 0x00000007 # P0.13 = A11
- mww 0xE0001038 0x00000007 # P0.14 = A12
- mww 0xE000103C 0x00000007 # P0.15 = A13
- mww 0xE0001048 0x00000007 # P0.18 = A14
- mww 0xE000104C 0x00000007 # P0.19 = A15
- mww 0xE0001050 0x00000007 # P0.20 = A16
- mww 0xE0001054 0x00000007 # P0.21 = A17
- mww 0xE0001058 0x00000007 # P0.22 = A18
- mww 0xE000105C 0x00000007 # P0.23 = A19
- mww 0xE0001238 0x00000007 # P2.14 = BLS0
- mww 0xE000123C 0x00000007 # P2.15 = BLS1
- mww 0xE0001300 0x00000007 # P3.0 = CS6
- mww 0xE0001304 0x00000007 # P3.1 = CS7
- mww 0xE0001130 0x00000007 # P1.12 = OE_N
- mww 0xE0001134 0x00000007 # P1.13 = WE_N
- mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1
- mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0
- mww 0x600000AC 0x00000005 # Bank6 WST1=5
- mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1
- mww 0x600000B0 0x00000006 # Bank6 WST2=6
- mww 0x600000A8 0x00000002 # Bank6 IDCY=2
- mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1
- mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0
- mww 0x600000C8 0x0000000A # Bank7 WST1=10
- mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1
- mww 0x600000CC 0x0000000C # Bank7 WST2=8
- mww 0x600000C4 0x00000002 # Bank7 IDCY=2
+ mww 0xE0001138 0x0000001F ;# P1.14 = D0
+ mww 0xE000113C 0x0000001F ;# P1.15 = D1
+ mww 0xE0001140 0x0000001F ;# P1.16 = D2
+ mww 0xE0001144 0x0000001F ;# P1.17 = D3
+ mww 0xE0001148 0x0000001F ;# P1.18 = D4
+ mww 0xE000114C 0x0000001F ;# P1.19 = D5
+ mww 0xE0001150 0x0000001F ;# P1.20 = D6
+ mww 0xE0001154 0x0000001F ;# P1.21 = D7
+ mww 0xE0001200 0x0000001F ;# P2.0 = D8
+ mww 0xE0001204 0x0000001F ;# P2.1 = D9
+ mww 0xE0001208 0x0000001F ;# P2.2 = D10
+ mww 0xE000120C 0x0000001F ;# P2.3 = D11
+ mww 0xE0001210 0x0000001F ;# P2.4 = D12
+ mww 0xE0001214 0x0000001F ;# P2.5 = D13
+ mww 0xE0001218 0x0000001F ;# P2.6 = D14
+ mww 0xE000121C 0x0000001F ;# P2.7 = D15
+ mww 0xE0001104 0x00000007 ;# P1.1 = A1
+ mww 0xE0001108 0x00000007 ;# P1.2 = A2
+ mww 0xE000110C 0x00000007 ;# P1.3 = A3
+ mww 0xE0001110 0x00000007 ;# P1.4 = A4
+ mww 0xE0001114 0x00000007 ;# P1.5 = A5
+ mww 0xE0001118 0x00000007 ;# P1.6 = A6
+ mww 0xE000111C 0x00000007 ;# P1.7 = A7
+ mww 0xE0001028 0x00000007 ;# P0.10 = A8
+ mww 0xE000102C 0x00000007 ;# P0.11 = A9
+ mww 0xE0001030 0x00000007 ;# P0.12 = A10
+ mww 0xE0001034 0x00000007 ;# P0.13 = A11
+ mww 0xE0001038 0x00000007 ;# P0.14 = A12
+ mww 0xE000103C 0x00000007 ;# P0.15 = A13
+ mww 0xE0001048 0x00000007 ;# P0.18 = A14
+ mww 0xE000104C 0x00000007 ;# P0.19 = A15
+ mww 0xE0001050 0x00000007 ;# P0.20 = A16
+ mww 0xE0001054 0x00000007 ;# P0.21 = A17
+ mww 0xE0001058 0x00000007 ;# P0.22 = A18
+ mww 0xE000105C 0x00000007 ;# P0.23 = A19
+ mww 0xE0001238 0x00000007 ;# P2.14 = BLS0
+ mww 0xE000123C 0x00000007 ;# P2.15 = BLS1
+ mww 0xE0001300 0x00000007 ;# P3.0 = CS6
+ mww 0xE0001304 0x00000007 ;# P3.1 = CS7
+ mww 0xE0001130 0x00000007 ;# P1.12 = OE_N
+ mww 0xE0001134 0x00000007 ;# P1.13 = WE_N
+ mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1
+ mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0
+ mww 0x600000AC 0x00000005 ;# Bank6 WST1=5
+ mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1
+ mww 0x600000B0 0x00000006 ;# Bank6 WST2=6
+ mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2
+ mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1
+ mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0
+ mww 0x600000C8 0x0000000A ;# Bank7 WST1=10
+ mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1
+ mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
+ mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-02 12:56:34 +0000