TCL scripts: add support for ST SPEAr310

Initial support for ST SPEAr310 and for the evaluation
board EVALSPEAr310 Rev. 2.0.
Scripts are split in generic for SPEAr3xx family and
specific for SPEAr310. This should easily allow adding
new members of the family.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>

4 files changed, 314 insertions, 0 deletions

diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl
new file mode 100644
index 00000000..df227642
--- /dev/null
+++ b/tcl/chip/st/spear/quirk_no_srst.tcl
@@ -0,0 +1,75 @@
+# Quirks to bypass missing SRST on JTAG connector
+# EVALSPEAr310 Rev. 2.0
+# http://www.st.com/spear
+#
+# Date:      2010-08-17
+# Author:    Antonio Borneo <borneo.antonio@gmail.com>
+
+# For boards that have JTAG SRST not connected.
+# We use "arm9 vector_catch reset" to catch button reset event.
+
+
+$_TARGETNAME configure -event reset-assert sp_reset_assert
+$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
+
+# keeps the name of the SPEAr target
+global sp_target_name
+set sp_target_name $_TARGETNAME
+
+# Keeps the argument of "reset" command (run, init, halt).
+global sp_reset_mode
+set sp_reset_mode ""
+
+# Helper procedure. Returns 0 is target is halted.
+proc sp_is_halted {} {
+	global sp_target_name
+
+	return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
+}
+
+# wait for reset button to be pressed, causing CPU to get halted
+proc sp_reset_deassert_post {} {
+	global sp_reset_mode
+
+	set bar(0) |
+	set bar(1) /
+	set bar(2) -
+	set bar(3) \\
+
+	poll on
+	puts "====> Press reset button on the board <===="
+	for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} {
+		puts -nonewline "$bar([expr $i & 3])\r"
+		sleep 200
+	}
+
+	# Remove catch reset event
+	arm9 vector_catch none
+
+	# CPU is halted, but we typed "reset run" ...
+	if { [string compare $sp_reset_mode "run"] == 0 } {
+		resume
+	}
+}
+
+# Override reset-assert, since no SRST available
+# Catch reset event
+proc sp_reset_assert {} {
+	arm9 vector_catch reset
+}
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+	global sp_reset_mode
+
+	set sp_reset_mode $mode
+
+	# We need to detect CPU get halted, so exit from halt
+	if { [sp_is_halted] } {
+		echo "Resuming CPU to detect reset"
+		resume
+	}
+
+	# Execute default init_reset{mode}
+	jtag arp_init-reset
+}
diff --git a/tcl/chip/st/spear/spear310.tcl b/tcl/chip/st/spear/spear310.tcl
new file mode 100644
index 00000000..b2c3676e
--- /dev/null
+++ b/tcl/chip/st/spear/spear310.tcl
@@ -0,0 +1,40 @@
+# Specific init scripts for ST SPEAr310 system on chip
+# http://www.st.com/spear
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo <borneo.antonio@gmail.com>
+
+
+proc sp310_init {} {
+	mww 0xfca80034 0x0000ffff	# enable all RAS clocks
+	mww 0xfca80040 0x00000000	# remove all RAS resets
+	mww 0xb4000008 0x00002ff4	# RAS function enable
+
+	mww 0xfca8013c 0x2f7bc210	# plgpio_pad_drv
+	mww 0xfca80140 0x017bdef6
+}
+
+proc sp310_emi_init {} {
+	# set EMI pad strength
+	mmw 0xfca80134 0x0e000000 0x00000000
+	mmw 0xfca80138 0x0e739ce7 0x00000000
+	mmw 0xfca8013c 0x00039ce7 0x00000000
+
+	# set safe EMI timing as in BootROM
+	#mww 0x4f000000 0x0000000f	# tAP_0_reg
+	#mww 0x4f000004 0x00000000	# tSDP_0_reg
+	#mww 0x4f000008 0x000000ff	# tDPw_0_reg
+	#mww 0x4f00000c 0x00000111	# tDPr_0_reg
+	#mww 0x4f000010 0x00000002	# tDCS_0_reg
+
+	# set fast EMI timing as in Linux
+	mww 0x4f000000 0x00000010	# tAP_0_reg
+	mww 0x4f000004 0x00000005	# tSDP_0_reg
+	mww 0x4f000008 0x0000000a	# tDPw_0_reg
+	mww 0x4f00000c 0x0000000a	# tDPr_0_reg
+	mww 0x4f000010 0x00000005	# tDCS_0_re
+
+	# 32bit wide, 8/16/32bit access
+	mww 0x4f000014 0x0000000e	# control_0_reg
+	mww 0x4f000094 0x0000003f	# ack_reg
+}
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
new file mode 100644
index 00000000..ea85d295
--- /dev/null
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -0,0 +1,79 @@
+# Generic init scripts for all ST SPEAr3xx family
+# http://www.st.com/spear
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo <borneo.antonio@gmail.com>
+
+
+# Initialize internal clock
+# Default:
+# - Crystal =  24 MHz
+# - PLL1    = 332 MHz
+# - PLL2    = 332 MHz
+# - CPU_CLK = 332 MHz
+# - DDR_CLK = 332 MHz async
+# - HCLK    = 166 MHz
+# - PCLK    =  83 MHz
+proc sp3xx_clock_default {} {
+	mww 0xfca00000 0x00000002	# set sysclk slow
+	mww 0xfca00014 0x0ffffff8	# set pll timeout to minimum (100us ?!?)
+
+	# DDRCORE disable to change frequency
+	set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
+	mww 0xfca8002c $val
+	mww 0xfca8002c $val # Yes, write twice!
+
+	# programming PLL1
+	mww 0xfca8000c 0xa600010c	# M=166 P=1 N=12
+	mww 0xfca80008 0x00001c0a	# power down
+	mww 0xfca80008 0x00001c0e	# enable
+	mww 0xfca80008 0x00001c06	# strobe
+	mww 0xfca80008 0x00001c0e
+	while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
+
+	# programming PLL2
+	mww 0xfca80018 0xa600010c	# M=166, P=1, N=12
+	mww 0xfca80014 0x00001c0a	# power down
+	mww 0xfca80014 0x00001c0e	# enable
+	mww 0xfca80014 0x00001c06	# strobe
+	mww 0xfca80014 0x00001c0e
+	while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
+
+	mww 0xfca80028 0x00000082	# enable plltimeen
+	mww 0xfca80024 0x00000511	# set hclkdiv="/2" & pclkdiv="/2"
+
+	mww 0xfca00000 0x00000004	# setting SYSCTL to NORMAL mode
+	while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
+
+	# Select source of DDR clock
+	#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
+	mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
+
+	# DDRCORE enable after change frequency
+	mmw 0xfca8002c 0x20000000 0x00000000
+}
+
+proc sp3xx_common_init {} {
+	mww 0xfca8002c 0xfffffff8	# enable clock of all peripherals
+	mww 0xfca80038 0x00000000	# remove reset of all peripherals
+
+	mww 0xfca800e4 0x78000008	# COMP1V8_REG
+	mww 0xfca800ec 0x78000008	# COMP3V3_REG
+
+	mww 0xfca80050 0x00000001	# Enable clk mem port 1
+
+	mww 0xfc000000 0x10000f5f	# init SMI and set HW mode
+	mww 0xfc000000 0x00000f5f
+
+	# Initialize Bus Interconnection Matrix
+	# All ports Round-Robin and lowest priority
+	mww 0xfca8007c 0x80000007
+	mww 0xfca80080 0x80000007
+	mww 0xfca80084 0x80000007
+	mww 0xfca80088 0x80000007
+	mww 0xfca8008c 0x80000007
+	mww 0xfca80090 0x80000007
+	mww 0xfca80094 0x80000007
+	mww 0xfca80098 0x80000007
+	mww 0xfca8009c 0x80000007
+}
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
new file mode 100644
index 00000000..eb1c4b02
--- /dev/null
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -0,0 +1,120 @@
+# Init scripts to configure DDR controller of SPEAr3xx
+# http://www.st.com/spear
+# Original values taken from XLoader source code
+#
+# Date:      2010-09-23
+# Author:    Antonio Borneo <borneo.antonio@gmail.com>
+
+
+proc sp3xx_ddr_init {ddr_type} {
+	if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
+		ddr_spr3xx_mt47h64m16_3_333_cl5_async
+		set ddr_size 0x08000000
+	## add here new DDR chip definition. Prototype:
+	#} elseif { $ddr_type == "?????" } {
+	#	?????
+	#	set ddr_size 0x?????
+	} else {
+		error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
+	}
+
+	# Check for single/double memory chip
+	# DDR starts at address 0x00000000
+	mww $ddr_size 0x87654321
+	mww 0x00000000 0x12345678
+	if {[expr [mrw 0x00000000] == 0x12345678 && [mrw $ddr_size] == 0x87654321]} {
+		puts [format \
+			"Double chip DDR memory. Total memory size 0x%08x byte" \
+			[expr 2 * $ddr_size]]
+	} else {
+		puts [format \
+			"Single chip DDR memory. Memory size 0x%08x byte" \
+			$ddr_size]
+	}
+}
+
+
+# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
+proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
+	# DDR_PAD_REG
+	mww 0xfca800f0 0x00003aa5
+
+	# Use "1:2 sync" only when DDR clock source is PLL1 and
+	# HCLK is half of PLL1
+	mww 0xfc600000 0x00000001	# MEMCTL_AHB_SET_00 # This is async
+	mww 0xfc600004 0x00000000	# MEMCTL_AHB_SET_01
+#	mww 0xfc600000 0x02020201	# MEMCTL_AHB_SET_00 # This is 1:2 sync
+#	mww 0xfc600004 0x02020202	# MEMCTL_AHB_SET_01
+
+	mww 0xfc600008 0x01000000	# MEMCTL_RFSH_SET_00
+	mww 0xfc60000c 0x00000101	# MEMCTL_DLL_SET_00
+	mww 0xfc600010 0x00000101	# MEMCTL_GP_00
+	mww 0xfc600014 0x01000000	# MEMCTL_GP_01
+	mww 0xfc600018 0x00010001	# MEMCTL_GP_02
+	mww 0xfc60001c 0x00000100	# MEMCTL_GP_03
+	mww 0xfc600020 0x00010001	# MEMCTL_GP_04
+	mww 0xfc600024 0x01020203	# MEMCTL_GP_05
+	mww 0xfc600028 0x01000102	# MEMCTL_GP_06
+	mww 0xfc60002c 0x02000202	# MEMCTL_AHB_SET_02
+	mww 0xfc600030 0x04040105	# MEMCTL_AHB_SET_03
+	mww 0xfc600034 0x03030302	# MEMCTL_AHB_SET_04
+	mww 0xfc600038 0x02040101	# MEMCTL_AHB_SET_05
+	mww 0xfc60003c 0x00000002	# MEMCTL_AHB_SET_06
+	mww 0xfc600044 0x03000405	# MEMCTL_DQS_SET_0
+	mww 0xfc600048 0x03040002	# MEMCTL_TIME_SET_01
+	mww 0xfc60004c 0x04000305	# MEMCTL_TIME_SET_02
+	mww 0xfc600050 0x0505053f	# MEMCTL_AHB_RELPR_00
+	mww 0xfc600054 0x05050505	# MEMCTL_AHB_RELPR_01
+	mww 0xfc600058 0x04040405	# MEMCTL_AHB_RELPR_02
+	mww 0xfc60005c 0x04040404	# MEMCTL_AHB_RELPR_03
+	mww 0xfc600060 0x03030304	# MEMCTL_AHB_RELPR_04
+	mww 0xfc600064 0x03030303	# MEMCTL_AHB_RELPR_05
+	mww 0xfc600068 0x02020203	# MEMCTL_AHB_RELPR_06
+	mww 0xfc60006c 0x02020202	# MEMCTL_AHB_RELPR_07
+	mww 0xfc600070 0x01010102	# MEMCTL_AHB_RELPR_08
+	mww 0xfc600074 0x01010101	# MEMCTL_AHB_RELPR_09
+	mww 0xfc600078 0x00000001	# MEMCTL_AHB_RELPR_10
+	mww 0xfc600088 0x0a0c0a00	# MEMCTL_DQS_SET_1
+	mww 0xfc60008c 0x0000023f	# MEMCTL_GP_07
+	mww 0xfc600090 0x00050a00	# MEMCTL_GP_08
+	mww 0xfc600094 0x11000000	# MEMCTL_GP_09
+	mww 0xfc600098 0x00001302	# MEMCTL_GP_10
+	mww 0xfc60009c 0x00001c1c	# MEMCTL_DLL_SET_01
+	mww 0xfc6000a0 0x7c000000	# MEMCTL_DQS_OUT_SHIFT
+	mww 0xfc6000a4 0x005c0000	# MEMCTL_WR_DQS_SHIFT
+	mww 0xfc6000a8 0x2b050e00	# MEMCTL_TIME_SET_03
+	mww 0xfc6000ac 0x00640064	# MEMCTL_AHB_PRRLX_00
+	mww 0xfc6000b0 0x00640064	# MEMCTL_AHB_PRRLX_01
+	mww 0xfc6000b4 0x00000064	# MEMCTL_AHB_PRRLX_02
+	mww 0xfc6000b8 0x00000000	# MEMCTL_OUTRANGE_LGTH
+	mww 0xfc6000bc 0x00200020	# MEMCTL_AHB_RW_SET_00
+	mww 0xfc6000c0 0x00200020	# MEMCTL_AHB_RW_SET_01
+	mww 0xfc6000c4 0x00200020	# MEMCTL_AHB_RW_SET_02
+	mww 0xfc6000c8 0x00200020	# MEMCTL_AHB_RW_SET_03
+	mww 0xfc6000cc 0x00200020	# MEMCTL_AHB_RW_SET_04
+	mww 0xfc6000d8 0x00000a24	# MEMCTL_TREF
+	mww 0xfc6000dc 0x00000000	# MEMCTL_EMRS3_DATA
+	mww 0xfc6000e0 0x5b1c00c8	# MEMCTL_TIME_SET_04
+	mww 0xfc6000e4 0x00c8002e	# MEMCTL_TIME_SET_05
+	mww 0xfc6000e8 0x00000000	# MEMCTL_VERSION
+	mww 0xfc6000ec 0x0001046b	# MEMCTL_TINIT
+	mww 0xfc6000f0 0x00000000	# MEMCTL_OUTRANGE_ADDR_01
+	mww 0xfc6000f4 0x00000000	# MEMCTL_OUTRANGE_ADDR_02
+	mww 0xfc600104 0x001c0000	# MEMCTL_DLL_DQS_DELAY_BYPASS_0
+	mww 0xfc600108 0x0019001c	# MEMCTL_DLL_SET_02
+	mww 0xfc60010c 0x00100000	# MEMCTL_DLL_SET_03
+	mww 0xfc600110 0x001e007a	# MEMCTL_DQS_SET_2
+	mww 0xfc600188 0x00000000	# MEMCTL_USER_DEF_REG_0
+	mww 0xfc60018c 0x00000000	# MEMCTL_USER_DEF_REG_1
+	mww 0xfc600190 0x01010001	# MEMCTL_GP_11
+	mww 0xfc600194 0x01000000	# MEMCTL_GP_12
+	mww 0xfc600198 0x00000001	# MEMCTL_GP_13
+	mww 0xfc60019c 0x00400000	# MEMCTL_GP_14
+	mww 0xfc6001a0 0x00000000	# MEMCTL_EMRS2_DATA_X
+	mww 0xfc6001a4 0x00000000	# MEMCTL_LWPWR_CNT
+	mww 0xfc6001a8 0x00000000	# MEMCTL_LWPWR_REG
+	mww 0xfc6001ac 0x00860000	# MEMCTL_GP_15
+	mww 0xfc6001b0 0x00000002	# MEMCTL_TPDEX
+	# MPMC START
+	mww 0xfc60001c 0x01000100
+}