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| author | Thomas Koeller <thomas.koeller@baslerweb.com> | 2010-08-10 14:56:42 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-08-12 08:59:02 +0200 |
| commit | 98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db (patch) | |
| tree | 3a4a7be46cf6709ff52e6558b3a75f1ce1738cea /tcl/target | |
| parent | a8c8c238f2dd1abe102f83bfa392ac40f313dd73 (diff) | |
| download | openocd_libswd-98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db.tar.gz openocd_libswd-98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db.tar.bz2 openocd_libswd-98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db.tar.xz openocd_libswd-98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db.zip | |
DM36x: Use enable bit for PLL pre-divider
The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/davinci.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 6c6769fa..b736c6ef 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -179,7 +179,7 @@ proc pll_v03_setup {pll_addr mult config} { mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr ($div - 1)] + set div [expr 0x8000 | ($div - 1)] mww [expr $pll_addr + 0x0114] $div } if { [dict exists $config postdiv] } { |