- added str912 test example, and test result

git-svn-id: svn://svn.berlios.de/openocd/trunk@410 b42882b7-edfa-0310-969c-e2dbd0fdcd60

6 files changed, 563 insertions, 0 deletions

diff --git a/testing/examples/STR912Test/prj/eclipse_ram.gdb b/testing/examples/STR912Test/prj/eclipse_ram.gdb
new file mode 100644
index 00000000..56a7091f
--- /dev/null
+++ b/testing/examples/STR912Test/prj/eclipse_ram.gdb
@@ -0,0 +1,21 @@
+target remote localhost:3333

+monitor reset

+monitor sleep 500

+monitor poll

+monitor soft_reset_halt

+monitor arm7_9 sw_bkpts enable

+

+# Set SRAM size to 96 KB

+monitor mww 0x5C002034 0x0197

+monitor mdw 0x5C002034

+

+# Set Flash, Bank0 size to 512 KB

+monitor mww 0x54000000 0xf

+

+load

+break main

+continue

+

+

+

+

diff --git a/testing/examples/STR912Test/prj/eclipse_rom.gdb b/testing/examples/STR912Test/prj/eclipse_rom.gdb
new file mode 100644
index 00000000..87d1abc0
--- /dev/null
+++ b/testing/examples/STR912Test/prj/eclipse_rom.gdb
@@ -0,0 +1,21 @@
+target remote localhost:3333

+monitor reset

+monitor sleep 500

+monitor poll

+monitor soft_reset_halt

+monitor arm7_9 force_hw_bkpts enable

+

+# Set SRAM size to 96 KB

+monitor mww 0x5C002034 0x0197

+monitor mdw 0x5C002034

+

+# Set Flash, Bank0 size to 512 KB

+monitor mww 0x54000000 0xf

+

+load

+break main

+continue

+

+

+

+

diff --git a/testing/examples/STR912Test/prj/str912_jtagkey.cfg b/testing/examples/STR912Test/prj/str912_jtagkey.cfg
new file mode 100644
index 00000000..7ba8dd24
--- /dev/null
+++ b/testing/examples/STR912Test/prj/str912_jtagkey.cfg
@@ -0,0 +1,45 @@
+#daemon configuration

+telnet_port 4444

+gdb_port 3333

+

+# tell gdb our flash memory map

+# and enable flash programming

+gdb_memory_map enable

+gdb_flash_program enable

+

+#interface

+interface ft2232

+ft2232_device_desc "Amontec JTAGkey A"

+ft2232_layout jtagkey

+ft2232_vid_pid 0x0403 0xcff8

+jtag_speed 1

+

+jtag_nsrst_delay 100

+jtag_ntrst_delay 100

+

+#use combined on interfaces or targets that can't set TRST/SRST separately

+reset_config trst_and_srst

+

+#jtag scan chain

+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)

+jtag_device 8 0x1 0x1 0xfe

+jtag_device 4 0x1 0xf 0xe

+jtag_device 5 0x1 0x1 0x1e

+

+#target configuration

+daemon_startup reset

+

+#target <type> <startup mode>

+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>

+target arm966e little reset_halt 1 arm966e

+run_and_halt_time 0 30

+

+target_script 0 gdb_program_config .\prj\str912_program.script

+

+working_area 0 0x50000000 16384 nobackup

+

+#flash bank str7x <base> <size> 0 0 <target#> <variant>

+flash bank str9x 0x00000000 0x00080000 0 0 0

+

+# For more information about the configuration files, take a look at:

+# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger

diff --git a/testing/examples/STR912Test/prj/str912_program.script b/testing/examples/STR912Test/prj/str912_program.script
new file mode 100644
index 00000000..07e366dc
--- /dev/null
+++ b/testing/examples/STR912Test/prj/str912_program.script
@@ -0,0 +1,9 @@
+str9x flash_config 0 4 2 0 0x80000

+flash protect 0 0 7 off

+

+

+

+

+

+

+

diff --git a/testing/examples/STR912Test/prj/str912_ram.ld b/testing/examples/STR912Test/prj/str912_ram.ld
new file mode 100644
index 00000000..0974b390
--- /dev/null
+++ b/testing/examples/STR912Test/prj/str912_ram.ld
@@ -0,0 +1,218 @@
+/***********************************************************************************

+*	Copyright 2005 Anglia Design

+*	This demo code and associated components are provided as is and has no warranty,

+*	implied or otherwise.  You are free to use/modify any of the provided

+*	code at your own risk in your applications with the expressed limitation

+*	of liability (see below)

+* 

+*	LIMITATION OF LIABILITY:   ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY

+*	LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR

+*	INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER

+*	THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

+*

+*	Author			: Spencer Oliver

+*	Web     		: www.anglia-designs.com

+*

+***********************************************************************************/

+

+/* Stack Sizes */

+

+	_STACKSIZE     = 1024;

+	_STACKSIZE_IRQ = 256;

+	_STACKSIZE_FIQ = 0;

+	_STACKSIZE_SVC = 1024;

+	_STACKSIZE_ABT = 0;

+	_STACKSIZE_UND = 0;

+	_HEAPSIZE      = 1024;

+

+/* Memory Definitions */

+

+MEMORY

+{

+	DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000

+}

+

+/* Section Definitions */

+

+SECTIONS

+{

+	/* first section is .text which is used for code */

+

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+}

+

diff --git a/testing/examples/STR912Test/prj/str912_rom.ld b/testing/examples/STR912Test/prj/str912_rom.ld
new file mode 100644
index 00000000..8cbb7f75
--- /dev/null
+++ b/testing/examples/STR912Test/prj/str912_rom.ld
@@ -0,0 +1,249 @@
+/***********************************************************************************

+*	Copyright 2005 Anglia Design

+*	This demo code and associated components are provided as is and has no warranty,

+*	implied or otherwise.  You are free to use/modify any of the provided

+*	code at your own risk in your applications with the expressed limitation

+*	of liability (see below)

+* 

+*	LIMITATION OF LIABILITY:   ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY

+*	LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR

+*	INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER

+*	THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

+*

+*	Author			: Spencer Oliver

+*	Web     		: www.anglia-designs.com

+*

+***********************************************************************************/

+

+/* Stack Sizes */

+

+	_STACKSIZE     = 1024;

+	_STACKSIZE_IRQ = 256;

+	_STACKSIZE_FIQ = 0;

+	_STACKSIZE_SVC = 1024;

+	_STACKSIZE_ABT = 0;

+	_STACKSIZE_UND = 0;

+	_HEAPSIZE      = 1024;

+

+/* Memory Definitions */

+

+MEMORY

+{

+	CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000

+	DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000

+}

+

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+

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+