diff options
| -rw-r--r-- | tcl/board/phytec_lpc3250.cfg | 88 | ||||
| -rw-r--r-- | tcl/target/lpc3250.cfg | 36 |
2 files changed, 124 insertions, 0 deletions
diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg new file mode 100644 index 00000000..78cb90de --- /dev/null +++ b/tcl/board/phytec_lpc3250.cfg @@ -0,0 +1,88 @@ +source [find target/lpc3250.cfg] + +jtag_nsrst_delay 200 +jtag_ntrst_delay 1 +jtag_khz 200 +reset_config trst_and_srst separate + +arm7_9 dcc_downloads enable + +$_TARGETNAME configure -event gdb-attach { reset init } + +$_TARGETNAME configure -event reset-start { + arm7_9 fast_memory_access disable + jtag_khz 200 +} + +$_TARGETNAME configure -event reset-end { + jtag_khz 6000 + arm7_9 fast_memory_access enable +} + +$_TARGETNAME configure -event reset-init { phytec_lpc3250_init } + +# Bare-bones initialization of core clocks and SDRAM +proc phytec_lpc3250_init { } { + # Set clock dividers + # ARMCLK = 266.5 MHz + # HCLK = 133.25 MHz + # PERIPHCLK = 13.325 MHz + mww 0x400040BC 0 + mww 0x40004050 0x140 + mww 0x40004040 0x4D + mww 0x40004058 0x16250 + + # Init PLLs + mww 0x40004044 0x006 + sleep 1 busy + mww 0x40004044 0x106 + sleep 1 busy + mww 0x40004044 0x006 + sleep 1 busy + mww 0x40004048 0x2 + + # Init SDRAM with 133 MHz timings + mww 0x40028134 0x00FFFFFF + mww 0x4002802C 0x00000008 + + mww 0x31080000 1 + mww 0x31080008 0 + mww 0x40004068 0x1C000 + mww 0x31080028 0x11 + + mww 0x31080400 0 + mww 0x31080440 0 + mww 0x31080460 0 + mww 0x31080480 0 + + # Delays + mww 0x31080030 1 + mww 0x31080034 6 + mww 0x31080038 10 + mww 0x31080044 1 + mww 0x31080048 9 + mww 0x3108004C 12 + mww 0x31080050 10 + mww 0x31080054 1 + mww 0x31080058 1 + mww 0x3108005C 0 + + mww 0x31080100 0x5680 + mww 0x31080104 0x302 + + # Init sequence + mww 0x31080020 0x193 + sleep 1 busy + mww 0x31080024 1 + mww 0x31080020 0x113 + sleep 1 busy + mww 0x31080020 0x013 + sleep 1 busy + mww 0x31080024 65 + mww 0x31080020 0x093 + mdw 0x80020000 + mww 0x31080020 0x013 + + # SYS_CTRL remapping + mww 0x40004014 1 +} diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg new file mode 100644 index 00000000..e902fb41 --- /dev/null +++ b/tcl/target/lpc3250.cfg @@ -0,0 +1,36 @@ +# lpc3250 config +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc3250 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x17900f0f +} + +if { [info exists SJCTAPID ] } { + set _SJCTAPID $SJCTAPID +} else { + set _SJCTAPID 0x1b900f0f +} + +jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0 + +proc power_restore {} { puts "Sensed power restore. No action." } +proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } |