diff options
| -rw-r--r-- | src/target/arm926ejs.c | 178 |
1 files changed, 89 insertions, 89 deletions
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 9cfdcdd5..a6dbcfe7 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -73,7 +73,7 @@ target_type_t arm926ejs_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm7_9_read_memory, @@ -81,7 +81,7 @@ target_type_t arm926ejs_target = .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -129,9 +129,9 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 u8 address_buf[2]; u8 nr_w_buf = 0; u8 access = 1; - + buf_set_u32(address_buf, 0, 14, address); - + jtag_add_end_state(TAP_RTI); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { @@ -178,12 +178,12 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[3].in_check_mask = NULL; fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - + jtag_add_dr_scan(4, fields, -1); fields[0].in_handler_priv = value; fields[0].in_handler = arm_jtag_buf_to_u32; - + /*TODO: add timeout*/ do { @@ -200,7 +200,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); #endif - + arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan); return ERROR_OK; @@ -218,10 +218,10 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u u8 address_buf[2]; u8 nr_w_buf = 1; u8 access = 1; - + buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - + jtag_add_end_state(TAP_RTI); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { @@ -268,7 +268,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[3].in_check_mask = NULL; fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - + jtag_add_dr_scan(4, fields, -1); /*TODO: add timeout*/ do @@ -303,9 +303,9 @@ int arm926ejs_examine_debug_reason(target_t *target) embeddedice_read_reg(dbg_stat); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - + debug_reason = buf_get_u32(dbg_stat->value, 6, 4); - + switch (debug_reason) { case 1: @@ -357,7 +357,7 @@ int arm926ejs_examine_debug_reason(target_t *target) retval = ERROR_TARGET_FAILURE; break; } - + return retval; } @@ -387,43 +387,43 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int /* read cp15 control register */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); jtag_execute_queue(); - + if (mmu) { /* invalidate TLB */ arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); - + cp15_control &= ~0x1U; } - + if (d_u_cache) { u32 debug_override; - /* read-modify-write CP15 debug override register + /* read-modify-write CP15 debug override register * to enable "test and clean all" */ arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); debug_override |= 0x80000; arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); - + /* clean and invalidate DCache */ arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); - /* write CP15 debug override register + /* write CP15 debug override register * to disable "test and clean all" */ debug_override &= ~0x80000; arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); - + cp15_control &= ~0x4U; } - + if (i_cache) { /* invalidate ICache */ arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); - + cp15_control &= ~0x1000U; } - + arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); } @@ -438,16 +438,16 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i /* read cp15 control register */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control |= 0x1U; - + if (d_u_cache) cp15_control |= 0x4U; - + if (i_cache) cp15_control |= 0x1000U; - + arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); } @@ -480,14 +480,14 @@ void arm926ejs_post_debug_entry(target_t *target) arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); - + LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", - arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); + arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); u32 cache_dbg_ctrl; - - /* read-modify-write CP15 cache debug control register + + /* read-modify-write CP15 cache debug control register * to disable I/D-cache linefills and force WT */ arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); cache_dbg_ctrl |= 0x7; @@ -505,10 +505,10 @@ void arm926ejs_pre_restore_context(target_t *target) arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr); arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr); arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far); - + u32 cache_dbg_ctrl; - - /* read-modify-write CP15 cache debug control register + + /* read-modify-write CP15 cache debug control register * to reenable I/D-cache linefills and disable WT */ arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); cache_dbg_ctrl &= ~0x7; @@ -521,35 +521,35 @@ int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; arm926ejs_common_t *arm926ejs; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm9tdmi = arm7_9->arch_info; if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) { return -1; } - + arm926ejs = arm9tdmi->arch_info; if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm9tdmi_p = arm9tdmi; *arm926ejs_p = arm926ejs; - + return ERROR_OK; } @@ -559,18 +559,18 @@ int arm926ejs_arch_state(struct target_s *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - - char *state[] = + + char *state[] = { "disabled", "enabled" }; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - + LOG_USER( "target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" @@ -581,9 +581,9 @@ int arm926ejs_arch_state(struct target_s *target) buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm926ejs->armv4_5_mmu.mmu_enabled], - state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], + state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); - + return ERROR_OK; } @@ -595,12 +595,12 @@ int arm926ejs_soft_reset_halt(struct target_s *target) arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - + if((retval = target_halt(target)) != ERROR_OK) { return retval; } - + long long then=timeval_ms(); int timeout; while (!(timeout=((timeval_ms()-then)>1000))) @@ -630,27 +630,27 @@ int arm926ejs_soft_reset_halt(struct target_s *target) LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } - + target->state = TARGET_HALTED; - + /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - + /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - + armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; - + arm926ejs_disable_mmu_caches(target, 1, 1, 1); arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - + return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } @@ -662,7 +662,7 @@ int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 c arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - + if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) return retval; @@ -689,14 +689,14 @@ int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 c int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm9tdmi_init_target(cmd_ctx, target); - + return ERROR_OK; - + } int arm926ejs_quit(void) { - + return ERROR_OK; } @@ -704,17 +704,17 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, in { arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; - + /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) */ arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); arm9tdmi->arch_info = arm926ejs; arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; - + arm7_9->post_debug_entry = arm926ejs_post_debug_entry; arm7_9->pre_restore_context = arm926ejs_pre_restore_context; - + arm926ejs->read_cp15 = arm926ejs_cp15_read; arm926ejs->write_cp15 = arm926ejs_cp15_write; arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1; @@ -725,22 +725,22 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, in arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches; arm926ejs->armv4_5_mmu.has_tiny_pages = 1; arm926ejs->armv4_5_mmu.mmu_enabled = 0; - + arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason; - + /* The ARM926EJ-S implements the ARMv5TE architecture which * has the BKPT instruction, so we don't have to use a watchpoint comparator */ arm7_9->arm_bkpt = ARMV5_BKPT(0x0); arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; - + return ERROR_OK; } int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) { arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - + arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant); return ERROR_OK; @@ -750,14 +750,14 @@ int arm926ejs_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm926ejs_cmd; - - + + retval = arm9tdmi_register_commands(cmd_ctx); - + arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands"); register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]"); - + register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>"); @@ -790,7 +790,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]"); return ERROR_OK; } - + opcode_1 = strtoul(args[0], NULL, 0); opcode_2 = strtoul(args[1], NULL, 0); CRn = strtoul(args[2], NULL, 0); @@ -801,13 +801,13 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); return ERROR_OK; } - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + if (argc == 4) { u32 value; @@ -820,7 +820,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, { return retval; } - + command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); } else @@ -844,18 +844,18 @@ int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; arm926ejs_common_t *arm926ejs; - + if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) { command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); return ERROR_OK; } - + return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); } int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -868,20 +868,20 @@ int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); } int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -894,20 +894,20 @@ int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); } int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -920,15 +920,15 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); } static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical) @@ -938,7 +938,7 @@ static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physic u32 cb; int domain; u32 ap; - + armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; @@ -961,7 +961,7 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled) { armv4_5_common_t *armv4_5 = target->arch_info; arm926ejs_common_t *arm926ejs = armv4_5->arch_info; - + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); |