diff options
Diffstat (limited to 'src/target/event')
| -rw-r--r-- | src/target/event/at91sam9260_reset.script | 58 | ||||
| -rw-r--r-- | src/target/event/zy1000_reset.script | 18 |
2 files changed, 76 insertions, 0 deletions
diff --git a/src/target/event/at91sam9260_reset.script b/src/target/event/at91sam9260_reset.script new file mode 100644 index 00000000..8390d72c --- /dev/null +++ b/src/target/event/at91sam9260_reset.script @@ -0,0 +1,58 @@ +mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
+mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+
+mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
+sleep 20 # wait 20 ms
+mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
+sleep 10 # wait 10 ms
+mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
+sleep 20 # wait 20 ms
+mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
+sleep 10 # wait 10 ms
+mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
+sleep 10 # wait 10 ms
+
+jtag_speed 0 # Increase JTAG Speed to 6 MHz
+arm7_9 dcc_downloads enable # Enable faster DCC downloads
+
+mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+mww 0xffffec04 0x09070806 # SMC_PULSE0
+mww 0xffffec08 0x000d000b # SMC_CYCLE0
+mww 0xffffec0c 0x00001003 # SMC_MODE0
+
+flash probe 0 # Identify flash bank 0
+
+mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
+mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
+
+mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+
+#mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+
+mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+mww 0x20000000 0
+mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+mww 0x20000000 0
+mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x4
+mww 0x20000000 0
+mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+mww 0x20000000 0
+mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+mww 0x20000000 0
+mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
+
diff --git a/src/target/event/zy1000_reset.script b/src/target/event/zy1000_reset.script new file mode 100644 index 00000000..d48eb402 --- /dev/null +++ b/src/target/event/zy1000_reset.script @@ -0,0 +1,18 @@ +reg cpsr 0x000000D3
+
+mww 0xFFE00000 0x0100273D
+mww 0xFFE00004 0x08002125
+mww 0xFFEe0008 0x02002125
+mww 0xFFE0000c 0x03002125
+mww 0xFFE00010 0x40000000
+mww 0xFFE00014 0x50000000
+mww 0xFFE00018 0x60000000
+mww 0xFFE0001c 0x70000000
+mww 0xFFE00020 0x00000001
+mww 0xFFE00024 0x00000000
+
+mww 0xFFFFF124 0xFFFFFFFF
+mww 0xffff0010 0x100
+mww 0xffff0034 0x100
+
+
|