diff options
Diffstat (limited to 'src/target/target/aduc702x.cfg')
| -rw-r--r-- | src/target/target/aduc702x.cfg | 36 |
1 files changed, 26 insertions, 10 deletions
diff --git a/src/target/target/aduc702x.cfg b/src/target/target/aduc702x.cfg index c9ef92cd..35f5ff32 100644 --- a/src/target/target/aduc702x.cfg +++ b/src/target/target/aduc702x.cfg @@ -1,6 +1,27 @@ ## -*- tcl -*- ## + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + + jtag_nsrst_delay 200 jtag_ntrst_delay 200 @@ -10,18 +31,13 @@ reset_config none ## JTAG scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID ## ## Target configuration ## -target create target0 arm7tdmi -endian little -chain-position 0 - -## software initiated reset (if your SRST isn't wired) -#proc target_0_reset {} { mwb 0x0ffff0230 04 } - -# use top 1k of SRAM for as temporary JTAG memory -#[new_target_name] configure -work-area-virt 0 -work-area-phys 0x11C00 -work-area-size 0x400 -work-area-backup 1 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME ## flash configuration flash bank aduc702x 0x80000 0x10000 2 2 0 @@ -37,5 +53,5 @@ proc watchdog_service {} { set watchdog_hdl [after 500 watchdog_service] } -[new_target_name] configure -event reset-halt-post { watchdog_service } -[new_target_name] configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl } +$_TARGETNAME configure -event reset-halt-post { watchdog_service } +$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl } |