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-rw-r--r--src/target/target/stm32.cfg47
1 files changed, 40 insertions, 7 deletions
diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg
index 1c80679e..c9581d49 100644
--- a/src/target/target/stm32.cfg
+++ b/src/target/target/stm32.cfg
@@ -1,5 +1,18 @@
# script for stm32
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
# jtag speed
jtag_khz 500
@@ -10,15 +23,35 @@ jtag_ntrst_delay 100
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-
-target create target0 cortex_m3 -endian little -chain-position 0
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.2
+ # Medium Density RevA
+ set _BSTAPID 0x06410041
+ # Rev B and Rev Z
+ set _BSTAPID 0x16410041
+ # High Density Devices, Rev A
+ set _BSTAPID 0x06414041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at: