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-rw-r--r--src/target/embeddedice.c24
-rw-r--r--src/target/etb.c68
-rw-r--r--src/target/etm.c19
3 files changed, 54 insertions, 57 deletions
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 59cd5624..69f3a768 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008,2009 Øyvind Harboe *
+ * Copyright (C) 2007-2010 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2008 by Spencer Oliver *
@@ -357,7 +357,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
/* bits 36:32 -- register */
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- fields[1].out_value[0] = reg_addr;
+ field1_out[0] = reg_addr;
fields[1].in_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
@@ -365,7 +365,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
/* bit 37 -- 0/read */
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- fields[2].out_value[0] = 0;
+ field2_out[0] = 0;
fields[2].in_value = NULL;
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
@@ -382,7 +382,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
* EICE_COMMS_DATA would read the register twice
* reading the control register is safe
*/
- fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+ field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
/* traverse Update-DR, reading but with no other side effects */
jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
@@ -413,12 +413,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+ field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- fields[2].out_value[0] = 0;
+ field2_out[0] = 0;
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -429,7 +429,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
* to avoid reading additional data from the DCC data reg
*/
if (size == 1)
- fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+ field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
fields[0].in_value = (uint8_t *)data;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -529,18 +529,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+ field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- fields[2].out_value[0] = 1;
+ field2_out[0] = 1;
fields[2].in_value = NULL;
while (size > 0)
{
- buf_set_u32(fields[0].out_value, 0, 32, *data);
+ buf_set_u32(field0_out, 0, 32, *data);
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
data++;
@@ -581,12 +581,12 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+ field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
- fields[2].out_value[0] = 0;
+ field2_out[0] = 0;
fields[2].in_value = NULL;
jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
diff --git a/src/target/etb.c b/src/target/etb.c
index 32808741..ba47c39a 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -55,14 +55,15 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr)
struct scan_field field;
field.num_bits = tap->ir_length;
- field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
- buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+ void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, new_instr);
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
- free(field.out_value);
+ free(t);
}
return ERROR_OK;
@@ -75,8 +76,9 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
struct scan_field field;
field.num_bits = 5;
- field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
- buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
+ void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+ field.out_value = t;
+ buf_set_u32(t, 0, field.num_bits, new_scan_chain);
field.in_value = NULL;
@@ -86,7 +88,7 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
etb->cur_scan_chain = new_scan_chain;
- free(field.out_value);
+ free(t);
}
return ERROR_OK;
@@ -181,13 +183,15 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
fields[0].in_value = NULL;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, 4);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, 4);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
@@ -195,13 +199,13 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
for (i = 0; i < num_frames; i++)
{
/* ensure nR/W reamins set to read */
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ buf_set_u32(&temp2, 0, 1, 0);
/* address remains set to 0x4 (RAM data) until we read the last frame */
if (i < num_frames - 1)
- buf_set_u32(fields[1].out_value, 0, 7, 4);
+ buf_set_u32(&temp1, 0, 7, 4);
else
- buf_set_u32(fields[1].out_value, 0, 7, 0);
+ buf_set_u32(&temp1, 0, 7, 0);
fields[0].in_value = (uint8_t *)(data + i);
jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
@@ -211,9 +215,6 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
jtag_execute_queue();
- free(fields[1].out_value);
- free(fields[2].out_value);
-
return ERROR_OK;
}
@@ -236,15 +237,17 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[0].check_mask = NULL;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
@@ -254,16 +257,13 @@ static int etb_read_reg_w_check(struct reg *reg,
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
*/
- buf_set_u32(fields[1].out_value, 0, 7, 0x0);
+ buf_set_u32(&temp1, 0, 7, 0x0);
fields[0].in_value = reg->value;
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
- free(fields[1].out_value);
- free(fields[2].out_value);
-
return ERROR_OK;
}
@@ -312,25 +312,23 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
etb_set_instr(etb_reg->etb, 0xc);
fields[0].num_bits = 32;
- fields[0].out_value = malloc(4);
- buf_set_u32(fields[0].out_value, 0, 32, value);
+ uint8_t temp0[4];
+ fields[0].out_value = temp0;
+ buf_set_u32(&temp0, 0, 32, value);
fields[0].in_value = NULL;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 1);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 1);
fields[2].in_value = NULL;
-
- free(fields[0].out_value);
- free(fields[1].out_value);
- free(fields[2].out_value);
-
return ERROR_OK;
}
diff --git a/src/target/etm.c b/src/target/etm.c
index 3850ced5..4f4bf9a4 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -514,15 +514,17 @@ static int etm_read_reg_w_check(struct reg *reg,
fields[0].check_mask = NULL;
fields[1].num_bits = 7;
- fields[1].out_value = malloc(1);
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ uint8_t temp1;
+ fields[1].out_value = &temp1;
+ buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
fields[2].num_bits = 1;
- fields[2].out_value = malloc(1);
- buf_set_u32(fields[2].out_value, 0, 1, 0);
+ uint8_t temp2;
+ fields[2].out_value = &temp2;
+ buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
@@ -535,9 +537,6 @@ static int etm_read_reg_w_check(struct reg *reg,
jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
- free(fields[1].out_value);
- free(fields[2].out_value);
-
return ERROR_OK;
}
@@ -592,19 +591,19 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
fields[0].num_bits = 32;
uint8_t tmp1[4];
fields[0].out_value = tmp1;
- buf_set_u32(fields[0].out_value, 0, 32, value);
+ buf_set_u32(tmp1, 0, 32, value);
fields[0].in_value = NULL;
fields[1].num_bits = 7;
uint8_t tmp2;
fields[1].out_value = &tmp2;
- buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+ buf_set_u32(&tmp2, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
uint8_t tmp3;
fields[2].out_value = &tmp3;
- buf_set_u32(fields[2].out_value, 0, 1, 1);
+ buf_set_u32(&tmp3, 0, 1, 1);
fields[2].in_value = NULL;
jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
generated by cgit v1.2.3 (git 2.46.0) at 2024-11-15 21:11:38 +0000