summaryrefslogtreecommitdiff
path: root/src/target
diff options
context:
space:
mode:
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm_disassembler.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 09024102..8a048cfc 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1247,7 +1247,7 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
}
/* catch opcodes with [27:25] = b011 */
- if ((opcode & 0x0e000000) == 0x04000000)
+ if ((opcode & 0x0e000000) == 0x06000000)
{
/* Undefined instruction */
if ((opcode & 0x00000010) == 0x00000010)