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-rw-r--r--tcl/board/hilscher_nxdb500sys.cfg40
-rw-r--r--tcl/board/hilscher_nxeb500hmi.cfg40
-rw-r--r--tcl/board/hilscher_nxhx10.cfg82
-rw-r--r--tcl/board/hilscher_nxhx50.cfg40
-rw-r--r--tcl/board/hilscher_nxhx500.cfg42
-rw-r--r--tcl/board/hilscher_nxsb100.cfg29
6 files changed, 273 insertions, 0 deletions
diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
new file mode 100644
index 00000000..48aff354
--- /dev/null
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -0,0 +1,40 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ halt
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads enable
+
+ sdram_fix
+
+ puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
+ mww 0x00100140 0
+ mww 0x00100144 0x03C13261
+ mww 0x00100140 0x030D0121
+
+ puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)"
+ mww 0x00100100 0x0201000E
+
+ flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME
+
+init
+reset init
diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
new file mode 100644
index 00000000..9accd98d
--- /dev/null
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -0,0 +1,40 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ halt
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads disable
+
+ sdram_fix
+
+ puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
+ mww 0x00100140 0
+ mww 0x00100144 0x03C23251
+ mww 0x00100140 0x030D0111
+
+ puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)"
+ mww 0x00100100 0x0101000E
+
+ flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
new file mode 100644
index 00000000..4a6b972a
--- /dev/null
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -0,0 +1,82 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx10.cfg]
+
+# Usually it is not needed to set srst_pulls_trst
+# but sometimes it does not work without it. If you encounter
+# problems try to line below
+# reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
+
+# Par. Flash can only be accessed if DIP switch on the board is set in proper
+# position and init_sdrambus was called. Don't call these functions if the DIP
+# switch is in invalid position, as some outputs may collide. This is why this
+# function is not called automatically
+proc flash_init { } {
+ puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+ mww 0x101C0100 0x01010008
+
+ flash probe 0
+}
+
+proc mread32 {addr} {
+ set value(0) 0
+ mem2array value 32 $addr 1
+ return $value(0)
+}
+
+proc init_clocks { } {
+ puts "Enabling all clocks "
+ set accesskey [mread32 0x101c0070]
+ mww 0x101c0070 [expr $accesskey]
+
+ mww 0x101c0028 0x00007511
+}
+
+proc init_sdrambus { } {
+ puts "Initializing external SDRAM Bus 16 Bit "
+ set accesskey [mread32 0x101c0070]
+ mww 0x101c0070 [expr $accesskey]
+ mww 0x101c0C40 0x00000050
+
+ puts "Configuring SDRAM controller for K4S561632E (32MB) "
+ mww 0x101C0140 0
+ sleep 100
+ #mww 0x101C0144 0x00a13262
+ mww 0x101C0144 0x00a13251
+ mww 0x101C0148 0x00000033
+ mww 0x101C0140 0x030d0121
+}
+
+$_TARGETNAME configure -event reset-init {
+ halt
+ wait_halt 1000
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads enable
+
+ init_clocks
+# init_sdrambus
+
+ puts ""
+ puts "-------------------------------------------------"
+ puts "Call 'init_clocks' to enable all clocks"
+ puts "Call 'init_sdrambus' to enable external SDRAM bus"
+ puts "-------------------------------------------------"
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init \ No newline at end of file
diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg
new file mode 100644
index 00000000..d129d12e
--- /dev/null
+++ b/tcl/board/hilscher_nxhx50.cfg
@@ -0,0 +1,40 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx50.cfg]
+
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ halt
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads enable
+
+ sdram_fix
+
+ puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+ mww 0x1C000140 0
+ mww 0x1C000144 0x00A12151
+ mww 0x1C000140 0x030D0001
+
+ puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+ mww 0x1C000100 0x01010008
+
+ flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg
new file mode 100644
index 00000000..3f2ff56e
--- /dev/null
+++ b/tcl/board/hilscher_nxhx500.cfg
@@ -0,0 +1,42 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ halt
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads enable
+
+ sleep 100
+
+ sdram_fix
+
+ puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+ mww 0x00100140 0
+ mww 0x00100144 0x03C23251
+ mww 0x00100140 0x030D0001
+
+ puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
+ mww 0x00100100 0x01010008
+
+ flash probe 0
+}
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
+flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
+
+init
+reset init
diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
new file mode 100644
index 00000000..f52af448
--- /dev/null
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -0,0 +1,29 @@
+################################################################################
+# Author: Michael Trensch (MTrensch@googlemail.com)
+################################################################################
+
+source [find target/hilscher_netx500.cfg]
+
+reset_config trst_and_srst
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ halt
+
+ arm7_9 fast_memory_access enable
+ arm7_9 dcc_downloads enable
+
+ sdram_fix
+
+ puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
+ mww 0x00100140 0
+ mww 0x00100144 0x03C23251
+ mww 0x00100140 0x030D0001
+
+}
+
+init
+reset init
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-23 01:26:11 +0000