diff options
Diffstat (limited to 'tcl/target/ti_dm6446.cfg')
| -rw-r--r-- | tcl/target/ti_dm6446.cfg | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg index cc23ad44..4dac3d5f 100644 --- a/tcl/target/ti_dm6446.cfg +++ b/tcl/target/ti_dm6446.cfg @@ -7,20 +7,18 @@ if { [info exists CHIPNAME] } { set _CHIPNAME dm6446 } -# -# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB -# are enabled without making ICEpick route ARM and ETB into the JTAG chain. -# Override by setting EMU01 to "-disable". -# -# Also note: when running without RTCK before the PLLs are set up, you -# may need to slow the JTAG clock down quite a lot (under 2 MHz). -# +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + source [find target/icepick.cfg] -set EMU01 "-enable" -#set EMU01 "-disable" # Subsidiary TAP: unknown ... must enable via ICEpick -jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable +jtag newtap $_CHIPNAME unknown -irlen 8 -disable jtag configure $_CHIPNAME.unknown -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 3" @@ -35,8 +33,7 @@ if { [info exists ETB_TAPID ] } { } else { set _ETB_TAPID 0x2b900f0f } -jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_ETB_TAPID $EMU01 +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" @@ -46,8 +43,7 @@ if { [info exists CPU_TAPID ] } { } else { set _CPU_TAPID 0x07926001 } -jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_CPU_TAPID $EMU01 +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" @@ -57,9 +53,12 @@ if { [info exists JRC_TAPID ] } { } else { set _JRC_TAPID 0x0b70002f } -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" +################ # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) # and the ETB memory (4K) are other options, while trace is unused. # Little-endian; use the OpenOCD default. |