diff options
Diffstat (limited to 'tcl/target/ti_dm6446.cfg')
| -rw-r--r-- | tcl/target/ti_dm6446.cfg | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg index cc23ad44..e96c3e15 100644 --- a/tcl/target/ti_dm6446.cfg +++ b/tcl/target/ti_dm6446.cfg @@ -20,7 +20,7 @@ set EMU01 "-enable" #set EMU01 "-disable" # Subsidiary TAP: unknown ... must enable via ICEpick -jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable +jtag newtap $_CHIPNAME unknown -irlen 8 -disable jtag configure $_CHIPNAME.unknown -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 3" @@ -35,8 +35,7 @@ if { [info exists ETB_TAPID ] } { } else { set _ETB_TAPID 0x2b900f0f } -jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_ETB_TAPID $EMU01 +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 jtag configure $_CHIPNAME.etb -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" @@ -46,8 +45,7 @@ if { [info exists CPU_TAPID ] } { } else { set _CPU_TAPID 0x07926001 } -jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_CPU_TAPID $EMU01 +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 jtag configure $_CHIPNAME.arm -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" @@ -57,8 +55,7 @@ if { [info exists JRC_TAPID ] } { } else { set _JRC_TAPID 0x0b70002f } -jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ - -expected-id $_JRC_TAPID +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) # and the ETB memory (4K) are other options, while trace is unused. |