diff options
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/lpc1768.cfg | 52 |
1 files changed, 27 insertions, 25 deletions
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index f0093ad4..182fb89d 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -1,4 +1,4 @@ -# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator +# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -6,12 +6,18 @@ if { [info exists CHIPNAME] } { set _CHIPNAME lpc1768 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK ] } { + set _CCLK $CCLK } else { - set _ENDIAN little + set _CCLK 4000 } - if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { @@ -23,29 +29,25 @@ jtag_nsrst_delay 200 jtag_ntrst_delay 200 # LPC2000 & LPC1700 -> SRST causes TRST -reset_config trst_and_srst srst_pulls_trst +reset_config srst_pulls_trst -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM) -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0 +target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -# REVISIT is there any good reason to have this reset-init event handler?? -# Normally they should set up (board-specific) clocking then probe the flash... -$_TARGETNAME configure -event reset-init { - # Force NVIC.VTOR to point to flash at 0 ... - # WHY? This is it's reset value; we run right after reset!! - mwb 0xE000ED08 0x00 -} - -# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region). -# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum] +# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000). +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 +# LPC1768 has 512kB of flash memory, managed by ROM code (including a +# boot loader which verifies the flash exception table's checksum). set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum - -# 4MHz / 6 = 666kHz, so use 500 -jtag_khz 500 +flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +# JTAG clock should be CCLK/6 (unless using adaptive clocking) +# CCLK is 4 MHz after reset, and until board-specific code (like +# a reset-init handler) speeds it up. +jtag_rclk [ expr 4000 / 6 ] +$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] } |