| Commit message (Collapse) | Author | Age | Files | Lines |
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reduce duplication. No change in behavior.
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dap_ap_select was used in the code at various points, but that can lead to
confusion, without any knowledge of what AP is really selected at some
points.
Some bugs derive from this (for example md/mw doesn't work well after
issueing "dap apsel" command).
Moving it to arm_adi_v5.c (using mem_ap_sel* functions instead of mem_ap_*)
make the code more clear and more easier to maintain.
In the future it should be made "static" to avoid its use outside arm_adi_v5
One further benefit is the various goto has been removed as well
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Remove duplicate inline that causes certain versions of gcc to choke.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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This patch adds read/write capability to memory addresses not
accessible through AHB-AP (for example "boot ROM code").
To select AHB or APB, a "dap apsel" command must be issued:
dap apsel 0 -> following memory accesses are through AHB
dap apsel 1 -> following memory accesses are through APB
NOTE: at the moment APB memory accesses are very slow, compared
to AHB accesses. Work has to be done to get it faster (for
example LDR/STR instead od LDRB/STRB)
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Save, select and restore AP in cortex_a9_step and cortex_a9_init_debug_access.
Fixes a bug where the wrong AP is selected after a reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Michal Demin <michaldemin@gmail.com>
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oops...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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PandaBoard REV EA1 (Panda Early Adopter Program) has a different ID.
This patch add alternate REV EA1 TAP id to configuration file
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Hello,
this patch add commands to access to x,y and p memory. For run time optimization some local jtag
function was changed to static inline.
Regards,
Mathias
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Also i have checked the input of this function and in many cases
a simple byte copy is possible.
I have added this check now and is it possible the buffer is
copied byte by byte and not bit by bit.
With byte boundary input the test looks like this:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.828559 new: 0.436191 diff: 6.392368
runtime (seconds): old: 6.853636 new: 0.430389 diff: 6.423247
runtime (seconds): old: 6.794985 new: 0.423065 diff: 6.371920
Without:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.370869 new: 5.552624 diff: 0.818245
runtime (seconds): old: 6.420730 new: 5.665887 diff: 0.754843
runtime (seconds): old: 6.583306 new: 5.599021 diff: 0.984285
Regards,
Mathias
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ready for wider testing and comments on basic erase + programming.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Hello,
this patch adds the missing cpu registers and the correct read/write register functions and fixed
most of the halt/step/resume issues. The complete missing error propagation was added.
+ fix tab/spaces
Regards,
Mathias
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Hello,
this patch add 24bit support to the target buffer functions and little/big endian functions.
Regards,
Mathias
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* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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If a handler for the reset-assert event it present, skip the usual reset
handling. This is needed, for example, for board-level resets.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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The user does not need to know or care about "command handlers".
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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ARM11 broke with aa61a3b3d8b6acad19050987835ec05f3d298bdb
as the code only checked for arm 7/9.
CFI probably needs work for non-ARM targets but perhaps
not adding working area memory to e.g. MIPS will give
the default slow CFI support.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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add target and build support for A9
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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ARM Cortex-A9 multi-core chips expose a single TAP/DAP which connects
to both cores. The '-coreid' option selects which core the target
should connect to.
Note that at present, OpenOCD can connect to either core, but not both
simulatenously, until ADI contexts can be shared.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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ahbap_debugport_init was queueing reads to a local stack variable but
didn't execute the queue before returning. Since the result of the reads
are not used anyway, it's better to pass NULL as the destination instead of
a dummy variable. I changed this throughout the function, even for the
reads that were actually executed.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Added a Perl script to contrib that uses the header files in StellarisWare complete Firmware Development Package provided by TI/Luminary to generate a new list of device IDs
Used Perl script and revision 6734 of TI/Luminary StellarisWare to update device IDs
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Hi,
I took the stm32x NOR flash driver and adapted it for the Ember EM357
chip. This chip is very similar to em351 and stm32w so the driver
should be easily extended to support those as well if anyone can get
their hands on some of those for testing.
changelog:
Added NOR flash driver em357
Best regards,
Erik Botö
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Find the flash controller by position since it is before the core,
not after it.
This fixes the problem that str9xpec enable_turbo (or any other
str9xpec command) did not work. (See my post in
http://forum.sparkfun.com/viewtopic.php?f=18&t=25542)
Signed-off-by: Santeri Salko <santeri.salko@gmail.com>
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the wrong index of argv. argv[0] is the command itself,
argv[1] the the transport to select.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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LOG_DEBUG() arguments are only evaluated when DEBUG logging
is enabled, do not use arguments that have side effects
like foo++.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Remove extra \n from LOG_DEBUG, LOG_INFO, and LOG_WARNING messages
Remove LOG_INFO_N
LOG_INFO_N was only used once and had a \n at the end
Change LOG_USER_N calls that end with \n to LOG_USER
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specific targets (setup_lpc<number>) take core clock and adapter clock as parameters. This way "constant" parameters (flash size and type, CPUTAPID, etc.) do not need to be copied if one wishes to change the "variable" parameters - like the core clock or adapter clock - in a board config file or somewhere else.
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
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Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
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Signed-off-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
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Fixed in many other places, and submitted in response to Øyvind's invitation.
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Add a working area that is preserved between calls to
mips_m4k_bulk_write_memory - this gives us a speed increase
of approx 3kb/sec during flash writes to the pic32mx.
This area is released during a resume/reset.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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