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* ARM semihosting: use breakpoint on ARM7Nicolas Pitre2009-12-041-7/+9
| | | | | | | | | | | | Fall back to software breakpoint when vector catch isn't available. Possible enhancements: - add extra optional command parameter to select high vectors - add extra optional command parameter to select hardware breakpoint Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM semihosting: work with both low and high vectorsNicolas Pitre2009-12-041-6/+4
| | | | | Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename nand.h to flash//nand/core.hZachary T Welch2009-12-0420-28/+33
| | | | | | | | | Rename nand.h as flash/nand/core.h, chase consumers. The public APIs need to be sorted out with imp.h, but this allows other changes to begin improving the separation between policy and mechanism. Moves #include <target/target.h> and #include "driver.h" into the internal headers or source files, removing it from <flash/nand/core.h>.
* move remaining nand helper filesZachary T Welch2009-12-048-11/+9
| | | | Move remaining NAND implementation files into src/flash/nand/.
* split nand.c into nand/{core,fileio,tcl}.cZachary T Welch2009-12-047-872/+1005
| | | | | | | Moves commands into nand/tcl.c and core implementation to 'nand/core.c' and 'nand/fileio.c'. Eliminates 'flash/nand.c'. Adds 'nand/imp.h' to share routines between TCL commands and core.
* split NAND driver handling into nand/driver.[ch]Zachary T Welch2009-12-045-104/+205
| | | | | | | This work parallels the NOR directory, encapsulating the NAND drivers into a separate file. This takes an extra step by encapsulating the type of data structure used to manage the drivers, allowing it to be changed from an array to a dynamic list in the future.
* ARM: doc updates for main headerDavid Brownell2009-12-041-3/+11
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell2009-12-046-11/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_algorithm as arm_algorithmDavid Brownell2009-12-0411-27/+27
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: misc generic cleanupDavid Brownell2009-12-044-13/+28
| | | | | | | | | | | Remove an undesirable use of the CPSR symbol ... it needs to vanish. Flag mode-to-number stuff as obsolete; say why ... should also vanish. Get rid of no-longer-used mode and state typedefs. Comment a few of the implicit ties to "classic ARM". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGICDavid Brownell2009-12-0412-19/+19
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: switch target_to_armv4_5() to target_to_arm()David Brownell2009-12-048-20/+18
| | | | | | And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_state_* as arm_state_*David Brownell2009-12-0412-23/+23
| | | | | | And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell2009-12-048-39/+39
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell2009-12-0416-141/+141
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell2009-12-0418-77/+77
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: report watchpoint trigger insnDavid Brownell2009-12-041-0/+18
| | | | | | | As with Cortex-A8, the WFAR register holds useful information that should be recorded and, where relevant, displayed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: basic watchpoint supportDavid Brownell2009-12-045-9/+102
| | | | | | Use the DPM watchpoint support; remove old incomplete stubs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: tweak TAP ops and debuggingDavid Brownell2009-12-042-23/+61
| | | | | | | | | | | | | | | | | | Tweak scanchain 7 debug messaging: - show register addresses in decimal, matching ARM docs; - remove some pointless noise Avoid some needless roundtrips: - skip SCAN_N when SCREG already holds that number (speeds up polling and other common operations) - avoid zeroing vcr twice on resume Show the IR opcode as a label ("RESTART") too; and in decimal, matching ARM docs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* reorder build order of src directoryZachary T Welch2009-12-041-1/+9
| | | | Descend into the library modules in order, from bottom-to-top.
* remove flash.h from treeZachary T Welch2009-12-0418-63/+4
| | | | | Remove the now vestigial <flash/flash.h> header from the tree, replacing a few references with <flash/nor/core.h>
* split flash.h into into flash/nor/*.hZachary T Welch2009-12-046-326/+358
| | | | | | | | | Move the bulk of the flash.h file into flash/nor/core.h, leaving an empty husk that will be removed in the next patch. The NOR driver structure is an implementation detail, so move it into its own private header file <flash/nor/driver.h> along with helper declaration for finding them by name.
* remove target.h from flash.hZachary T Welch2009-12-0421-20/+31
| | | | | The flash.h header does not require the target.h header file, but its implementation source files do. Move it to flash/nor/imp.h.
* split NOR and NAND flash headersZachary T Welch2009-12-044-12/+15
| | | | | Moves common flash errors to <flash/common.h> to decouple these two mostly unrelated trees of code.
* eliminate src/flash/flash.cZachary T Welch2009-12-043-221/+187
| | | | | Move remaining NOR flash implemenation into flash/nor/core.c Removes flash.c from the build, leaving only its header to split.
* add flash/nor/drivers.cZachary T Welch2009-12-044-55/+79
| | | | | Encapsulates access to the flash_drivers array, providing a base of operations for future dynamic driver module loading features.
* move more nor flash implementation detailsZachary T Welch2009-12-045-999/+1011
| | | | | | | | Splits the exec mode commands out of flash.c into the flash/nor/ files. The routines used by these high-level commands are moved into nor/core.c, with their internal declarations placed in nor/imp.h. Fixes distribution of <flash/nor/core.h> header.
* ARM: semihosting entry cleanupDavid Brownell2009-12-041-8/+39
| | | | | | | | | Clean up arm_semihosting() entry a bit, comment some issues and just which SVC opcodes are getting intercepted. Microcontroller profile cores will need a new entry, since they use BKPT instead (and don't have either SVC mode or an SPSR register). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove semihosting globalsDavid Brownell2009-12-045-33/+48
| | | | | | | | Store a flag and errno in in "struct arm". Have "poll" output report when semihosting is active. Shrink some of the affected lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* User's Guide: more semihosting infoDavid Brownell2009-12-041-2/+21
| | | | | | | | List it in the concept index, in the section about target software changes a project might want to consider, and in the section about debug messaging. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* bootstrap: stop execution upon errorØyvind Harboe2009-12-041-0/+3
| | | | | | | When tools are not installed, exit immediately. This makes the error messages clearer. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* add flash/nor/core.[ch]Zachary T Welch2009-12-045-62/+149
| | | | | | | | | | | | | | | The newly moved flash TCL routines access the internals of the module too much. Fix the layering issues by adding new core NOR flash APIs: <flash/nor/core.h>: - flash_driver_find_by_name() - self-descriptive <flash/nor/imp.h>: - flash_bank_add() - encapsulates adding banks to bank list - flash_bank_list() - encapsulates retreiving bank list This allows the externs in flash/nor/imp.h to be removed, and these mechanisms may now be re-used by other flash module code.
* add flash/nor/{tcl.c,imp.h} from flash/flash.cZachary T Welch2009-12-044-175/+235
| | | | | | Moves the top-level 'flash' command handlers into flash/nor/tcl.c, with flash/nor/imp.h providing an internal implementation header to share non-public API components.
* separate Jim from jtag/core.cZachary T Welch2009-12-042-11/+11
| | | | | | After previous efforts, only one Jim routine remained in jtag/core.c, and moving it to jtag/tcl.c painlessly finishes separating these layers. The headers need separating, but the implementation is clean.
* switch 'rm' command away from using JimZachary T Welch2009-12-041-18/+11
| | | | | Commands that do not need to use Jim should be registered as high-level command handlers.
* check top-level command registrationsZachary T Welch2009-12-041-16/+34
| | | | | | | When calling module_register_commands, the return value needs to be checked for failures. Instead of duplicating code, use an array of function pointers to the identical registration functions to iterate over during startup.
* allow 'jtag init' to be run in any modeZachary T Welch2009-12-041-1/+1
| | | | Help alleviate further potential problems with interactive startup.
* target: cygwin build fixesDavid Brownell2009-12-042-4/+10
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* zy1000: FPGA revC wipØyvind Harboe2009-12-041-5/+19
| | | | | | | The bug in revC register memory access is pretty much cornered now. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* basic ARM semihosting supportNicolas Pitre2009-12-036-0/+528
| | | | | | | | | | | | | | | | | | | | Semihosting enables code running on an ARM target to use the I/O facilities on the host computer. The target application must be linked against a library that forwards operation requests by using the SVC instruction that is trapped at the Supervisor Call vector by the debugger. The "hosted" library version provided with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example. This is currently available for ARM9 processors, but any ARM variant should be able to support this with little additional work. Tested using binaries compiled with Sourcery G++ Lite 2009q1-161 and ARM RVCT 3.0. [dbrownell@users.sourceforge.net: doc tweaks, NEWS] Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* doxygen: remove some warningsDavid Brownell2009-12-032-1/+2
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Make ARM NAND I/O operations aware of last opDean Glazeski2009-12-031-4/+13
| | | | | | | | | Updates the ARM NAND I/O code to look at and update the op field of arm_nand_data to reflect the last operation performed. It uses this field to copy the correct code to the target in the case where the struct is used for reads and writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM NAND I/O interface updateDean Glazeski2009-12-033-7/+39
| | | | | | | | | | | Modify the arm_nand_data struct to better support both read and write operations while using the same struct. An additional field was added, and initialized, to record the last operation so that the correct code can be loaded to the working area. [dbrownell@users.sourceforge.net: merge init patch, tweak GPL note] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* NAND page command refactoring.Dean Glazeski2009-12-032-59/+35
| | | | | | | | | Created a new function that handles sending a command and the address information for pages to a NAND device. [dbrownell@users.sourceforge.net: tweaked line lengths, name 'oob_only'] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: tweak arch_state()David Brownell2009-12-031-10/+4
| | | | | | | | | Punt to the armv4_5_arch_state() for all the common stuff, to shrink code and so we will get any improvements it provides. Don't hide watchpoint status if we happen to be in "abort" mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-037-100/+60
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use shared DSCR bit namesDavid Brownell2009-12-033-42/+24
| | | | | | | | | | | | | For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: make DSCR bit defs sharableDavid Brownell2009-12-033-33/+43
| | | | | | | | | | | | | | | | Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix another init regressionDavid Brownell2009-12-031-4/+7
| | | | | | | | | | | | | | | This makes Beagle work again, instead of losing horribly because the JTAG event handlers are no longer able to e.g. "runtest". I get the previous quirky behavior ... comes up OK but "reset halt" somewhat mysteriously makes it all better. (Instead of nothing being able to work at all...) However, I'm still seeing: The 'init' command must be used before 'init'. That seems to come from invoking "jtag init", sometime after it gets mapped to "ocd_jtag init", according to debug message traces. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix double 'init' regressionZachary T Welch2009-12-031-1/+1
| | | | | | To prevent regression in the behavior of 'init', we allow it to run in any mode. If provided with -c init and with -c noinit, then the second init at startup caused a spurious mode failure. Let 'init' handle it.
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