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* target: add basic dsp563xx supportmkdorg@users.sourceforge.net2009-12-159-1/+1340
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* zy1000: keep up with command.h cleanupØyvind Harboe2009-12-151-5/+15
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* command: retire obsolete macroØyvind Harboe2009-12-151-11/+0
| | | | | | | COMMAND_REGISTER() was only used transiently during code conversion. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* imx31: move srst delay into config scriptØyvind Harboe2009-12-151-0/+2
| | | | | | reset init/run now works again. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM11: improved reset supportDavid Brownell2009-12-141-48/+55
| | | | | | | | | | | | | | Teach ARM11 how to use: - the new "reset-assert" event - vector catch to implement "reset halt" - use SRST more like other cores do - ... including leaving post-SRST delays up to config scripts This gives OMAP2420 the ability to reset, and doesn't seem to cause new iMX31 problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassemble STM correctlyDavid Brownell2009-12-141-2/+5
| | | | | | There is no "STMMIDA" instruction. There is however "STMDAMI". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* lm3748: use new Stellaris config fileDavid Brownell2009-12-142-33/+1
| | | | | | Use the new file, and remove the old target/lm3s3748.cfg one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Common target file for Stellaris chipsYegor Yefremov2009-12-141-0/+49
| | | | | | | | | Common target.cfg file for LM3S CPU family [dbrownell@users.sourceforge.net: rename, generalize more] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stellaris: device IDsEric Wetzel2009-12-141-150/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I added the remaining devices and device IDs to stellaris.c, and removed several devices that don't exist on the Stellaris web page. Additionally, I found a few devices with duplicate IDs ... the DID1 Version Number for LM3Sxxx parts have DID1 Version = 0x0, and for LM3Sxxxx have DID1 Version = 0x1. So I extended the comparison to use the VER and FAM fields from DID1 also. ID=0x33: LM3S812 (DID1v0) and LM3S2616 (DID1v1) ID=0x39: LM3S808 (DID1v0) and LM3S2276 (DID1v1) These are the parts I removed from the file for lack of documentation (no data sheet to confirm part ID): LM3S318, LM3S1101, LM3S1108, LM3S1615, LM3S1616, LM3S2016, LM3S2101, LM3S2108, LM3S3759, LM3S3768, LM3S5757, LM3S5767, LM3S5768, LM3S5769, LM3S6815, LM3S6816, LM3S6915, LM3S6916, LM3S6111, LM3S6118. Also, sort devices according to part number. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* jtag: add '-ignore-version' optionDavid Brownell2009-12-144-6/+44
| | | | | | | | | | Add a "-ignore-version" to "jtag newtap" which makes the IDCODE comparison logic optionally ignore version differences. Update the "scan_chain" command to illustrate this by showing the "*" character instead of the (ignored) version nibble. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target files shouldn't #include <target/...h>David Brownell2009-12-1325-39/+38
| | | | | | | | | | | Make these ".h" files adopt the same policy the ".c" files already follow: don't use <subsystem/...h> syntax for private interfaces. If we ever get reviewed/supported "public" interfaces they should come exclusively from some include/... directory; that'll be the time to switch to <...> syntax for any subsystem's own interfaces. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: further shrink Jim-awarenessDavid Brownell2009-12-134-7/+10
| | | | | | | | | | | | | Don't include <helper/jim.h> from target.h ... not everything which touches targets needs to be able to talk to Jim. Plus, most files include this header by another path. Also, switch the affected files to use the classic sequence for #included files: all <framework/headers.h> first, then the "local_headers.h". This helps prevent growth of problematic layering, by minimizing entanglement. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC2000: rename "r13_svc" as "sp_svc"David Brownell2009-12-121-1/+1
| | | | | | This driver didn't get updated when the name changed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: avoid pointless status returnsDavid Brownell2009-12-112-16/+11
| | | | | | | | For some routines that only returned ERROR_OK and where the caller never checked ... don't bother. Remove some noise, and bugfix some comments. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add missing call to add new NAND devicesZachary T Welch2009-12-112-0/+4
| | | | | I forgot to add a call to the newly factored nand_device_add(), along with its forward declaration.
* fix 'write_image' usage informationZachary T Welch2009-12-111-1/+1
| | | | | The 'flash write_image' command erroneously listed the bank number, when it actually uses target addresses to do that lookup for the user.
* ARM DPM: support updating HW breakpointsDavid Brownell2009-12-112-52/+75
| | | | | | | | | | | Abstract the DPM breakpoint and watchpoint data structures to have a shared core for housekeeping. Abstract the code updating the watchpoint registers so that it can be used to update breakpoint registers. Then do so, when something has set up the breakpoint state used by this code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassembly fixes for LDC/STC/MRRC/MCRRDavid Brownell2009-12-111-18/+33
| | | | | | | Properly detect all of these, including the "2" variants; and bugfix parameter display for LDC and STC. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: minor cleanup, mostly ITR commentsDavid Brownell2009-12-112-28/+43
| | | | | | | | | | | | | ITR register handling seemed to be giving me problems, so I updated the comments to better say what the code is trying to do ... and to note the preconditions (one of which seems to be an issue) as listed in the ARM1136 TRM. Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code; all the callers already specify an exit path, since this register isn't usable with such vague semantics. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* server: add server_preinit which is called before config file is parsed.Spencer Oliver2009-12-113-3/+14
| | | | | | | This fixes the issue under native win32 of the socket interface not being enabled (via WSAStartup) before init is called from a script. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* build: fix cygwin build warningsSpencer Oliver2009-12-111-1/+1
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* gdb_server: use more local variables in inner loop of fetching packetstiny ↵Øyvind Harboe2009-12-111-31/+73
| | | | | | | | | | | | | | | | | | refactoring to allow optimisation of inner loops Some profiling information for arm7 16MHz GDB load operation shows gdb_get_packet_inner() near the very top. Each sample counts as 0.01 seconds. % cumulative self self total time seconds seconds calls Ts/call Ts/call name 52.91 2.27 2.27 embeddedice_write_dcc 11.89 2.78 0.51 gdb_get_packet_inner 8.86 3.16 0.38 memcpy 3.26 3.30 0.14 idle_thread_main(unsigned int) 3.03 3.43 0.13 cyg_in_cksum Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* gdb_server: make struct gdb_connection privateØyvind Harboe2009-12-112-19/+21
| | | | | | it is only used inside gdb_server.c Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* optimisation: tiny optimisation for embedded iceØyvind Harboe2009-12-111-6/+5
| | | | | | | use two shift operations instead of three to set embedded ice register. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded hosts: optimize common code path for core arm operationsØyvind Harboe2009-12-112-46/+66
| | | | | | | avoid fn call for the if check on whether anything needs to be done. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* anotyer cygwin compile fixDavid Brownell2009-12-101-1/+2
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* zy1000: revc FPGA now worksØyvind Harboe2009-12-102-30/+6
| | | | | | remove kludge code. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: update arm_opcodes.h copyrightDavid Brownell2009-12-091-0/+3
| | | | | | | I neglected to copy Magnus' copyright when I moved several declarations from the ARMv7-M header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stellaris: flash protection updates, minor fixesDavid Brownell2009-12-092-68/+119
| | | | | | | | | | | | | | | | | | | | | | | | | Bugfix the read side of flash protection: - read the right register(s)! - handle more than 64K - record the results in the right places - don't display garbage. Partially bugfix the write side: - use 2KB lock regions instead of 1KB pages (!) - validate input range - don't try to _remove_ protection (it's write-once) - #define values we'll need to commit writes. - ... still doesn't handle pages over 64KB mark, or commit writes And minor cleanup and fixes: - get rid of some forward decls - properly locate a doxygen comment - fix some bad indentation - remove superfluous #include - add a new part ID (many are still missing) - make the downloaded algorithm code be read-only Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Comment and doxygen fixesDavid Brownell2009-12-095-30/+25
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ETM: only include oocd_trace.h when tracing enabled.Spencer Oliver2009-12-091-0/+3
| | | | | | Fixes build issue on systems that do not have <termios.h>, eg native win32. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Fix compilation error with gcc 4.4.1Rafael Campos Las Heras2009-12-081-0/+1
| | | | Signed-off-by: Rafael Campos Las Heras <methril@gmail.com>
* target: remove more exit() callsDavid Brownell2009-12-082-9/+2
| | | | | | | | These were all basically "can't happen" cases ... like having state be corrupted by an alpha particle after the previous check for whether a value was in-range. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove needless "extern"sDavid Brownell2009-12-084-24/+8
| | | | | | | | | | Most of these happened to be in the target.h file. Some of those are associated with symbols that could be removed at some point ... e.g. NVP_ASSERT/true and its sibling NVP_DEASSERT/false. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: move 'extern' decls to *.h filesDavid Brownell2009-12-085-15/+15
| | | | | | | | The exception being declarations for drivers. Those should be split out in some clean way -- like driver add/remove calls made by initialization code -- but that's for another day. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: cygwin complile fixesDavid Brownell2009-12-081-4/+6
| | | | | | | It's as if despite integers being 32-bits, GCC refuses to convert a "uint32_t" to one of them. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* zy1000: some background info on the zy1000 file.Øyvind Harboe2009-12-081-0/+25
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* minidriver: fix inline capability of minidriverØyvind Harboe2009-12-0811-48/+94
| | | | | | | | | | | Low latency low CPU processing power systems(embedded) will benefit greatly from being able to inline certain jtag_add_xxx() fn's. The trick is that this has to be done in such a way as to allow implementing an OpenOCD API with a shared library(eventually) on a PC hosted OpenOCD. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* zy1000: remove unecessary includeØyvind Harboe2009-12-081-4/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* build: add build/src to include pathØyvind Harboe2009-12-0812-10/+25
| | | | | | This allows including generated include files. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: cope with stupidheaded compilerDavid Brownell2009-12-071-2/+1
| | | | | | | | Some versions of GCC don't understand that if you mask with 0x3 then have cases 0-3, it's not possible for a variable assigned in all those branches to have no value at end-of-case. Feh. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: list number of HW breakpoints/watchpointsDavid Brownell2009-12-074-7/+49
| | | | | | | | | | | | | | | When starting up, say how many hardware breakpoints and watchpoints are available on various targets. This makes it easier to tell GDB how many of those resources exist. Its remote protocol currently has no way to ask OpenOCD for that information, so it must configured by hand (or not at all). Update the docs to mention this; remove obsolete "don't do this" info. Presentation of GDB setup information is still a mess, but at least it calls out the three components that need setup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: add debug_reason_name()David Brownell2009-12-075-8/+19
| | | | | | | | Provide and use debug_reason_name() instead of expecting targets to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and the code becomes more clear too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: don't clone arm_arch_state() codeDavid Brownell2009-12-074-33/+8
| | | | | | | | | | | Have various ARM cores delegate to arm_arch_state() to display basic information, instead of duplicating that logic. This shrinks the code, makes them all report when semihosting is active, and highlights which data are specific to this core. (Like ARM720 not having separate instruction and data caches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* User's Guide: add quickie setup notesDavid Brownell2009-12-071-2/+41
| | | | | | | | | | | | | Add a brief "setup with no customization" note showing the how easily things can work if standard OpenOCD config scripts already exist. We've had some new users comment that this information is needlessly hard to find, so that starting to use OpenOCD is more difficult than it should be. Plus describe a few other issues that come up when setting up an OpenOCD server. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: use <target/arm.h> not armv4_5.hDavid Brownell2009-12-0724-200/+231
| | | | | | | | | | | | | | Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-0715-32/+34
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-0718-249/+281
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove mrc_opcode(), use MRC() or MCR()David Brownell2009-12-073-20/+32
| | | | | | | | | | | | Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where arm*20t should have used it, ARMV4_5_MCR() instead. Basically, *writing* coprocessor registers shouldn't have used the *read* opcode ... and both should stick to standard opcode constructors, not rearranging parameter sequence any more than already needed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: disassemble two more v6+ instructionsDavid Brownell2009-12-071-12/+71
| | | | | | | | | | | The SRS and RFE instructions speed exception entry/exit by making it easy to save and restore PC and SPSR. This handles both ARM and Thumb2 encodings. Fix minor PLD goofage; that "should never reach this point" can't happen, so remove it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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