summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM: fix target address when disassembling Thumb BLXNicolas Pitre2009-10-271-0/+1
| | | | | | | | A Thumb BLX instruction is branching to ARM code, and therefore the first 2 bits of the target address must be cleared. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Signalyzer: H2 and H4 supportOleg Seiljus2009-10-272-1/+810
| | | | | | | | | | This patch includes partial support for these new JTAG adapters. More complete support will require updates to the libftdi code, for EEPROM access. [dbrownell@users.sourceforge.net: fix whitespace, linelen, etc ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Signalyzer: new config filesOleg Seiljus2009-10-273-0/+33
| | | | | | Add configs for H2, H4, LITE. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix Thumb mode handling when single-stepping register based branch insnsNicolas Pitre2009-10-261-22/+33
| | | | | | | | | | | | | | | | | | | Currently, OpenOCD is always caching the PC value without the T bit. This means that assignment to the PC register must clear that bit and set the processor state to Thumb when it is set. And when the PC register value is transferred to another register or stored into memory then the T bit must be restored. Discussion: It is arguable if OpenOCd should have preserved the original PC value which would have greatly simplified this code. The processor state could then be obtained simply by getting at bit 0 of the PC. This however would require special handling elsewhere instead since the T bit is not always relevant (like when PC is used with ALU insns or as an index with some addressing modes). It is unclear which way would be simpler in the end. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: allow proper single stepping of Thumb BL and BLX instructionsNicolas Pitre2009-10-261-0/+12
| | | | | | | | | | | | | | Whenever an unconditional branch with the H bits set to 0b10 is met, the offset must be combined with the offset from the following opcode and not ignored like it is now. A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder would be a simpler solution. That might be true when single-stepping of Thumb2 code is implemented. But for now this appears to be the simplest solution to fix Thumb1 support. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: call thumb_pass_branch_condition() only for actual branch opcodesNicolas Pitre2009-10-261-8/+6
| | | | | | | | | | | | | | Calling it first with every opcodes and then testing if the opcode was indeed a branch instruction is wasteful and rather strange. If ever thumb_pass_branch_condition() has side effects (say, like printing a debugging traces) then the result would be garbage for most Thumb instructions which have no condition code. While at it, let's make the nearby code more readable by reducing some of the redundant brace noise and reworking the error handling construct. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ft2232: less noise with _DEBUG_JTAG_IO_David Brownell2009-10-261-1/+0
| | | | Don't log "Yes, I'm *still* in TAP_IDLE" every seven runtest clocks.
* JTAG: "jtag newtap ..." cleanupDavid Brownell2009-10-261-7/+2
| | | | | | Get rid of needless variable, improve and shrink diagnostic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: force reset configDavid Brownell2009-10-261-0/+4
| | | | | These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG.
* omap3530: target reset/init improvementsDavid Brownell2009-10-261-15/+25
| | | | | | | | | | | | | | | | | Now I can issue "reset halt" and have everything act smoothly; the vector_catch hardware is obviously not kicking in, but the rest of the reset sequence acts sanely. - TAP "setup" event enables the DAP, not omap3_dbginit (resolving a chicken/egg bug I noted a while back) - Remove stuff from omap3_dbginit which should never be used in event handlers - Cope better with slow clocking during reset Also, stop hard-wiring the target name: use the input params in the standard way, and set up $_TARGETNAME as an output param. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: "dap info" gets more readableDavid Brownell2009-10-261-33/+268
| | | | | | | | | | | | | | Make the "dap info" output more comprehensible: - Don't show CIDs unless they're incorrect (only four bits matter) - For CoreSight parts, interpret the part type - Interpret the part number - Show all five PID bytes together - Other minor cleanups Also some whitespace fixes, and shrink a few overlong source lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Fix incorrect line endingsSpencer Oliver2009-10-2630-27885/+27885
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Merge branch 'master' of ↵David Brownell2009-10-261-0/+5
|\ | | | | | | ssh://dbrownell@openocd.git.sourceforge.net/gitroot/openocd/openocd
| * Idea for adding watchpoint masks.Øyvind Harboe2009-10-261-0/+5
| |
* | balloon3 board base configWookey2009-10-261-0/+13
| | | | | | | | | | | | | | | | | | | | | | This is the very basic board config for the balloon3 board cpu JTAG channel. The rest of the config comprises another 14 .cfg files which I suspect openocd doesn't really want all of. I'm still not sure how to deal with this. I'll post another mail/patch to discuss. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* | SVF: fix parsing hex strings containing leading '0' charactersMichael Roth2009-10-261-0/+4
|/ | | | | | | | | Ignore leading '0' characters on hex strings. For example a bit pattern consisting of 6 bits could be written as 3f, 03f or 003f and so on. Signed-off-by: Michael Roth <mroth@nessie.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* JTAG: simple autoprobingDavid Brownell2009-10-262-14/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic autoprobing support for the JTAG scan chains which cooperate. To use, you can invoke OpenOCD with just: - interface spec: "-f interface/...cfg" - possibly with "-c 'reset_config ...'" for SRST/TRST - possibly with "-c 'jtag_khz ...'" for the JTAG clock Then set up config files matching the reported TAPs. It doesn't declare targets ... just TAPs. So facilities above the JTAG and SVF/XSVF levels won't be available without a real config; this is almost purely a way to generate diagnostics. Autoprobe was successful with most boards I tested, except ones incorporating C55x DSPs (which don't cooperate with this scheme for IR length autodetection). Here's what one multi-TAP chip reported, with the "Warn:" prefixes removed: clock speed 500 kHz There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..." AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..." AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..." AUTO auto0.tap - use "... -irlen 4" AUTO auto1.tap - use "... -irlen 4" AUTO auto2.tap - use "... -irlen 6" no gdb ports allocated as no target has been specified The patch tweaks IR setup a bit, so we can represent TAPs with undeclared IR length. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* minor fixes to TODO listDavid Brownell2009-10-251-5/+5
|
* fix syntax of mww phys.Øyvind Harboe2009-10-255-44/+44
|
* check if mmu is enabled before using mmu code pathØyvind Harboe2009-10-251-1/+1
|
* ARM: rename "arm9tdmi vector_catch" to "arm9 ..."David Brownell2009-10-254-17/+11
| | | | | | And update doc accordingly. That EmbeddedICE register was introduced for ARM9TDMI and then carried forward into most new chips that use EmbeddedICE.
* JTAG: jtag_tap_init() bugfixesDavid Brownell2009-10-251-9/+18
| | | | | | | Stop allocating three bytes per IR bit, and cope somewhat better with IR lengths over 32 bits. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* xscale: always reload handler after resetDavid Brownell2009-10-252-19/+11
| | | | | | | | | | | | | | | | | | | | Remove needless debug handler state. - "handler_installed" became wrong as soon as the second TRST+SRST reset was issued ... so the handler was never reloaded after the reset removed it from the mini-icache. This fixes the bug where subsequent resets fail on PXA255 (if the first one even worked, which is uncommon). Other XScale chips would have problems too; PXA270 seems to have, IXP425 maybe not. - "handler_running" was never tested; it's pointless. Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset. It was no more valid than the XScale's mini-icache. (Though ... such invalidations might be better done in "SRST asserted" callbacks.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* vector_catch and watchpoint TODO items.Øyvind Harboe2009-10-241-0/+6
|
* arm9tdmi vector_catch: reserved means "don't use"David Brownell2009-10-233-4/+5
| | | | | | | Bit 5 shouldn't be used. Remove all support for modifying it. Matches the exception vector table, of course ... more than one bootloader uses that non-vector to help distinguish valid boot images from random garbage in flash.
* Improve help for arm9 vector_catch.Øyvind Harboe2009-10-231-1/+3
|
* Remove debug output that could cause compile warnings.Øyvind Harboe2009-10-231-2/+0
|
* mcr/mrc interface work. Implemented for arm926ejs and arm720t. mcr/mrc ↵Øyvind Harboe2009-10-236-12/+241
| | | | commands added.
* Embedded ICE version is now dumped with debug_level 1Øyvind Harboe2009-10-231-2/+2
|
* jtag: clean up TAP state name handlingDavid Brownell2009-10-233-68/+63
| | | | | | | | | | | | Some cosmetic cleanup, and switch to a single table mapping between state names and symbols (vs two routines which only share that state with difficulty). Get rid of TAP_NUM_STATES, and some related knowledge about how TAP numbers are assigned. Later on, this will help us get rid of more such hardwired knowlege. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* SVF: clean up, mostly for TAP state name handlingDavid Brownell2009-10-235-80/+68
| | | | | | | | | | | | | | | | | | | | | - Use the name mappings all the other code uses: + name-to-state ... needed to add one special case + state-to-name - Improve various diagnostics: + don't complain about a "valid" state when the issue is actually that it must be "stable" + say which command was affected - Misc: + make more private data and code be static + use public DIM() not private dimof() + shorten the affected lines Re the mappings, this means we're more generous in inputs we accept, since case won't matter. Also our output diagnostics will be a smidgeon more informative, saying "RUN/IDLE" not just "IDLE" (emphasizing that there can be side effects). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Ferocion: fix corruption of r0 when resuming Thumb modeNicolas Pitre2009-10-221-2/+1
| | | | | | | | The wrong variable (pc instead of r0) was used. Furthermore, someone did cover this error by stupidly silencing the compiler warning that occurred before a dummy void reference to r0 was added to the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* have "reg" command print cache names tooDavid Brownell2009-10-221-0/+2
| | | | | | | When dumping over 100 registers (as on most ARM9 + ETM cores), aid readability by splitting them into logical groups. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ETM: rename registers, doc tweaksDavid Brownell2009-10-223-50/+73
| | | | | | | | | | | | | | | The register names are perversely not documented as zero-indexed, so rename them to match that convention. Also switch to lowercase suffixes and infix numbering, matching ETB and EmbeddedICE usage. Update docs to be a bit more accurate, especially regarding what the "trigger" event can cause; and to split the issues into a few more paragraphs, for clarity. Make "configure" helptext point out that "oocd_trace" is prototype hardware, not anything "real". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* disable ZY1000's UART forwarding test code.Øyvind Harboe2009-10-221-1/+10
|
* mww_phys retired. Replaced by generic mww phys in target.cØyvind Harboe2009-10-216-95/+44
|
* virt2phys is now implemented by target.c globally, retire target specific ↵Øyvind Harboe2009-10-211-15/+0
| | | | documentation.
* retire obsolete mXY_phys commands. Handled by generic memory read/modify ↵Øyvind Harboe2009-10-215-341/+0
| | | | commands and target read/write physical memory callbacks.
* read/write physical target fn'sØyvind Harboe2009-10-212-0/+53
|
* add support for target_read/write_phys_memory callbacks.Øyvind Harboe2009-10-211-2/+27
|
* Added target_read/write_phys_memory() fn's. mdX/mwX commands updated to ↵Øyvind Harboe2009-10-213-16/+94
| | | | support phys flag to specify bypassing of MMU.
* Merge branch 'master' of ↵Øyvind Harboe2009-10-211-2/+37
|\ | | | | | | ssh://gowinex@openocd.git.sourceforge.net/gitroot/openocd/openocd into HEAD
| * Retire obsolete and superfluous implementations of virt2phys in each target. ↵Øyvind Harboe2009-10-214-129/+0
| | | | | | | | This is done in a polymorphic implementation in target.c
| * First cut at implementing software breakpoints for mmu read only memoryØyvind Harboe2009-10-211-2/+37
| |
* | Retire obsolete and superfluous implementations of virt2phys in each target. ↵Øyvind Harboe2009-10-214-129/+0
|/ | | | This is done in a polymorphic implementation in target.c
* Defined target_write_memory() to be able to handle implementing breakpoints ↵Øyvind Harboe2009-10-211-0/+24
| | | | for read only ram(e.g. MMU write protected.
* eCos synthetic target updates.Øyvind Harboe2009-10-212-2/+13
|
* XSVF: use svf_add_statemove()David Brownell2009-10-206-68/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | XSVF improvements: - Layer parts of XSVF directly over SVF, calling svf_add_statemove() instead of expecting jtag_add_statemove() to conform to the SVF/XSVF requirements (which it doesn't). This should improve XSTATE handling a lot; it removes most users of jtag_add_statemove(), and the comments about how it should really do what svf_add_statemove() does. - Update XSTATE logic to be a closer match to the XSVF spec. The main open issue here is (still) that this implementation doesn't know how to build and submit paths from single-state transitions ... but now it will report that error case. - Update the User's Guide to mention the two utility scripts for working with XSVF, and to mention the five extension opcodes. Handling of state transition paths is, overall, still a mess. I think they should all be specified as paths not unlike SVF uses, and compiled to the bitstrings later ... so that we can actually make sense of the paths. (And see the extra clocks, detours through RUN, etc.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Removed unused interface_jtag_set_end_state and wrote down some notes on ↵Øyvind Harboe2009-10-204-13/+7
| | | | TCP/IP client/server scheme.
* Added the faux flash driver and target. Used for testing.Øyvind Harboe2009-10-205-1/+186
|
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-26 20:28:04 +0000