| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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all at91sam9 are nearly the same except sram and soc name
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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this will allow us to use multiple jlink at the same time as when
the USB-Address is specified the PID change from 0x0101 to
(0x101 + usb_adress)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The default pid of the segger is 0x0101
But when you change the USB Address it will also
pid = ( usb_address > 0x4) ? 0x0101 : (0x101 + usb_address)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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useful for debugging without access to hardware to e.g.
regression test, reproduce memory corruption problems,
etc.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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It wasn't previously possible to silence the output.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Useful to do something *real quick* after a SRST deassert.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This patch fix a possible read buffer overflow in ft2232_execute_queue.
Also the correct read queue size for libftdi and libftd2xx was added and
and tested.
In function ft2232_write a uninitialized value was initialized because we
don't know if this value was set in the ftdi api call.
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add new mem_ap_sel_* functions (as was made for cortex_a9)
see commit: 779005f43dc372de937dfd4b445f31d882b98eca
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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tested with jlink sam-ice v5 while loading barebox
(gdb) load
Loading section .text, size 0x2f190 lma 0x21f00000
Loading section .rodata, size 0x931c lma 0x21f2f190
Loading section .data, size 0x29e8 lma 0x21f384ac
Loading section .barebox_cmd, size 0x78c lma 0x21f3ae94
Loading section .barebox_initcalls, size 0x80 lma 0x21f3b620
Start address 0x21f00000, load size 243360
Transfer rate: 26 KB/sec, 13520 bytes/write.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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it will allow to be at the highest speed of the jlink without touching the
board or cpu config
tested on sam-ice v5 and at91rm9200-ek
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
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This patch add rudimentary gdb support. The gdb register list
order is corrected. All registers are now 32bit width. Events are
send to signalize gdb the current target status. Resume and step
function was corrected to consider a modified pc register. Read/write
memory now support L memory type, this means a memory with alternating
y/x memory words. The memspace variable, used by gdb, is now observed
before a default memory access is initiated. Dummy functions for breakpoint
and watchpoint are added.
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Use the http protocol for git2cl module, as it makes it easier for the
firewall safe mirror to keep all submodules firewall safe.
Signed-off-by: Edgar Grimberg <edgar.grimberg@gmail.com>
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stm32-discovery evaluation board (STM32F100RBTB6):
reading device id register (0xE0042000) returns 0x10010420
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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This patch tries to make some order in "apsel" mess.
"dap apsel" command was quite useless (and broken) by itself.
With this patch we can use it to select between AHB or APB memory access
(previous patch 05ab8bdb813acdcd74afa71d6656c2df816cb230 was somehow broken).
- moves member apsel (in struct adiv5_dap) to ap_current
- adds apsel member
this strange choice is made trying to keep coherence in "dap apsel" command
and to keep compatibility with other code (for example cortex_a8).
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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This patch move the dsp563xx_target_create function to the
related code block. Also the target examine function was added
and the register cache is initialized in a separate function. The
missing functionality to invalidate the x memory context on memory
writes was also added.
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This patch change the return value on a jtag communication error
to TARGET_UNKNOWN because this function should return the current
target status and not a error code from the underlying api call.
Also the validity of the jtag_status is extended to all static
bits in this value.
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write in resume and step function - add more conditional branch handling
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Based on the lpc3180 driver, but released as a separate driver for two reasons:
1) I don't have an lpc3180 to test it against, so it might unintentionally break compatibility.
2) It's using a different OOB layout than lpc3180.
Rewritten so that it no longer borrows code from the NXP CDL library. Instead borrowing code from the u-boot port to lpc32xx, written by Kevin Wells.
Tested on lpc3250 (Hitex LPC3250-Stick). OOB layout is compatible with LPCLinux.
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be flushed after the command
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memory transfer
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I've been working on Rodrigo on adding support to flash
Freescale dsp56800e devices and have been looking at the
dsp563xx code. I think the define for the JTAG CLAMP
instruction in dsp563xx_once.c is incorrect. It should
be 0x05 according the Freescale AN2074 (and is also
0x05 in the dsp568xx according to AN1935). It won't
actually change anything in OpenOCD since this define
is not used anywhere (as far as I can tell).
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reduce duplication. No change in behavior.
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dap_ap_select was used in the code at various points, but that can lead to
confusion, without any knowledge of what AP is really selected at some
points.
Some bugs derive from this (for example md/mw doesn't work well after
issueing "dap apsel" command).
Moving it to arm_adi_v5.c (using mem_ap_sel* functions instead of mem_ap_*)
make the code more clear and more easier to maintain.
In the future it should be made "static" to avoid its use outside arm_adi_v5
One further benefit is the various goto has been removed as well
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Remove duplicate inline that causes certain versions of gcc to choke.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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This patch adds read/write capability to memory addresses not
accessible through AHB-AP (for example "boot ROM code").
To select AHB or APB, a "dap apsel" command must be issued:
dap apsel 0 -> following memory accesses are through AHB
dap apsel 1 -> following memory accesses are through APB
NOTE: at the moment APB memory accesses are very slow, compared
to AHB accesses. Work has to be done to get it faster (for
example LDR/STR instead od LDRB/STRB)
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Save, select and restore AP in cortex_a9_step and cortex_a9_init_debug_access.
Fixes a bug where the wrong AP is selected after a reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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Signed-off-by: Michal Demin <michaldemin@gmail.com>
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oops...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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PandaBoard REV EA1 (Panda Early Adopter Program) has a different ID.
This patch add alternate REV EA1 TAP id to configuration file
Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Hello,
this patch add commands to access to x,y and p memory. For run time optimization some local jtag
function was changed to static inline.
Regards,
Mathias
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Signed-off-by: Luca Ellero <lroluk@gmail.com>
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Also i have checked the input of this function and in many cases
a simple byte copy is possible.
I have added this check now and is it possible the buffer is
copied byte by byte and not bit by bit.
With byte boundary input the test looks like this:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.828559 new: 0.436191 diff: 6.392368
runtime (seconds): old: 6.853636 new: 0.430389 diff: 6.423247
runtime (seconds): old: 6.794985 new: 0.423065 diff: 6.371920
Without:
buf_set_buf 0x02000000 iteration test:
runtime (seconds): old: 6.370869 new: 5.552624 diff: 0.818245
runtime (seconds): old: 6.420730 new: 5.665887 diff: 0.754843
runtime (seconds): old: 6.583306 new: 5.599021 diff: 0.984285
Regards,
Mathias
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ready for wider testing and comments on basic erase + programming.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Hello,
this patch adds the missing cpu registers and the correct read/write register functions and fixed
most of the halt/step/resume issues. The complete missing error propagation was added.
+ fix tab/spaces
Regards,
Mathias
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Hello,
this patch add 24bit support to the target buffer functions and little/big endian functions.
Regards,
Mathias
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* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.
Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
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