| Commit message (Collapse) | Author | Age | Files | Lines |
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This address the >32 bit problem with drscan
also added a check for bypass in the execute since this will manifest itself
as a memory corruption when this check helps to debug the problem alot easier
git-svn-id: svn://svn.berlios.de/openocd/trunk@794 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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PC hosted OpenOCD.
git-svn-id: svn://svn.berlios.de/openocd/trunk@647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon.
- now checks for User Thread Mode and Thread mode when halted.
- removed repeated function declarations from command.c
- cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit
git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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git-svn-id: svn://svn.berlios.de/openocd/trunk@523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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https://lists.berlios.de/pipermail/openocd-development/2008-January/000665.html
(thanks to oyvind Harboe for the patch)
git-svn-id: svn://svn.berlios.de/openocd/trunk@260 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- fixed several uses of uninitialized bits (Thanks to Vincent Palatin for finding and fixing these bugs)
git-svn-id: svn://svn.berlios.de/openocd/trunk@145 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- fixed arm926ej-s CP15 register access handling
- correctly identify SYSCLK source in LPC3180 NAND flash controller driver
git-svn-id: svn://svn.berlios.de/openocd/trunk@139 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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configuration
- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- str75x flash support (Thanks to Spencer Oliver)
- correct reporting of T-Bit in CPSR (Thanks to John Hartman for reporting this)
- core-state (ARM/Thumb) can be switched by modifying CPSR
- fixed bug in gdb_server register handling
- register values > 32-bit should now be supported
- several minor fixes and enhancements
git-svn-id: svn://svn.berlios.de/openocd/trunk@100 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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Michael Fischer) - you still need to install GiveIO (not part of OpenOCD)
- Added state-move support to ftd2xx and bitbang JTAG drivers (required for XScale, possibly useful for other targets, too)
- various fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@78 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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git-svn-id: svn://svn.berlios.de/openocd/trunk@64 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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