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* jtag: retire tap fieldØyvind Harboe2010-03-081-4/+4
| | | | | | | | | | | | | | | | | jtag_add_dr/ir_scan() now takes the tap as the first argument, rather than for each of the fields passed in. The code never exercised the path where there was more than one tap being scanned, who knows if it even worked. This simplifies the implementation and reduces clutter in the calling code. use jtag_add_ir/dr_plain_scan() for more fancy situations. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: keep a handle to the PCDavid Brownell2010-02-211-1/+1
| | | | | | | | | | | | | | | | Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: per-core options should not be globalDavid Brownell2010-02-211-33/+32
| | | | | | | | | | Address some FIXME comments by getting rid of globals, moving per-core parameters in the existing per-core data structure. This will matter most whenever there are multiple ARM11 cores, e.g. ARM11 MPcore chips, but in general is just cleanup. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* core arm11: Silence logs at level 3 if there is no activityEdgar Grimberg2010-01-251-1/+1
| | | | | | | | If the target and openocd are idling, the log should normally be silent at level 3. (Given no verbose logging options.) Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: fix breakpoints with GDBDavid Brownell2010-01-221-9/+15
| | | | | | | | | | | This fixes a bug whereby GDB's breakpoints weren't activated. The root cause is a confused interface to resume(). Fix by almost ignoring the "handle breakpoints" parameter; it only seems related to the case of skipping breakpoint-at-PC. Update a few coments to clarify what's happening. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: help/usage updatesDavid Brownell2010-01-071-12/+17
| | | | | | | | | | | | | | | | | Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Uupdate some helptext to be more accurate. Fix the User's Guide in a few places to be more consistent (mostly to use brackets not parentheses) and to recognize that parameter may be entirely optional (in which case the command just displays output, and changes nothing). Also reference NXP, not Philips, for LPC chips. Don't use "&function"; functions are like arrays, their address is their name. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: recognize ARM11 MPCoreDavid Brownell2009-12-201-5/+11
| | | | | | | And add my copyright. MPCore is untested, but it's the only other ARM11 core to care about. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: improved reset supportDavid Brownell2009-12-141-48/+55
| | | | | | | | | | | | | | Teach ARM11 how to use: - the new "reset-assert" event - vector catch to implement "reset halt" - use SRST more like other cores do - ... including leaving post-SRST delays up to config scripts This gives OMAP2420 the ability to reset, and doesn't seem to cause new iMX31 problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: minor cleanup, mostly ITR commentsDavid Brownell2009-12-111-15/+13
| | | | | | | | | | | | | ITR register handling seemed to be giving me problems, so I updated the comments to better say what the code is trying to do ... and to note the preconditions (one of which seems to be an issue) as listed in the ARM1136 TRM. Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code; all the callers already specify an exit path, since this register isn't usable with such vague semantics. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: rename some generic routinesDavid Brownell2009-12-071-3/+3
| | | | | | | | | | | | | | | | Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move opcode macros to <target/arm_opcodes.h>David Brownell2009-12-071-0/+1
| | | | | | | | | | | | | | | Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: report watchpoint trigger insnDavid Brownell2009-12-041-0/+18
| | | | | | | As with Cortex-A8, the WFAR register holds useful information that should be recorded and, where relevant, displayed. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: basic watchpoint supportDavid Brownell2009-12-041-1/+2
| | | | | | Use the DPM watchpoint support; remove old incomplete stubs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: tweak TAP ops and debuggingDavid Brownell2009-12-041-2/+3
| | | | | | | | | | | | | | | | | | Tweak scanchain 7 debug messaging: - show register addresses in decimal, matching ARM docs; - remove some pointless noise Avoid some needless roundtrips: - skip SCAN_N when SCREG already holds that number (speeds up polling and other common operations) - avoid zeroing vcr twice on resume Show the IR opcode as a label ("RESTART") too; and in decimal, matching ARM docs. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM DPM: share debug reason logicDavid Brownell2009-12-031-17/+7
| | | | | | | | | | | | | | | | | | No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use shared DSCR bit namesDavid Brownell2009-12-031-20/+22
| | | | | | | | | | | | | For the bits now defined in "arm_dpm.h", switch to the shared DSCR_* symbol and remove the ARM11_DSCR_* version. Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_* sibling symbol. (Note: for both ARM11 and Cortex-A8, this should arguably be enabled by default when single stepping.) Remove some other unused declarations in "arm11.h". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* change #include "time_support.h" to <helper/time_support.h>Zachary T Welch2009-12-031-1/+1
| | | | | | | | | | | | Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
* ARM11: don't expose DSCRDavid Brownell2009-12-021-171/+7
| | | | | | | | | | | Remove the remaining extra copy of DSCR, and the register cache of which it was a part. That cache wasn't a very safe, or even necessary, idea; it was essentialy letting debugger-private state be manipulated by Tcl code that couldn't know how to do it right. This makes the "reg" output of an ARM11 resemble what most other ARM cores produce ... forward motion in the "make ARM11 work like the rest of the ARM cores" Jihad!
* ARM11: store a clean copy of DSCRDavid Brownell2009-12-021-59/+41
| | | | | | | Just store a clean copy of DSCR in the per-CPU struct, so we trivially pass a pointer to a recent copy. This replaces the previous "last_dscr" and cleans up most of the related calling conventions ... but it doesn't remove the other DSCR copy.
* ARM11: don't expose WDTRDavid Brownell2009-12-021-13/+7
| | | | | | | | | Don't expose the WDTR register through the register cache any more. If anyone wants Tcl scripts to be able to use DCC based communication with app code in the target, this wouldn't do it. Bugfix: don't trust the Tcl-accessible version of DSCR to flag whether WDTR needs to be restored when resuming.
* ARM11: don't expose RDTRDavid Brownell2009-12-021-14/+7
| | | | | | | | | Don't expose the RDTR register through the register cache any more. If anyone wants Tcl scripts to be able to use DCC based communication with app code in the target, this wouldn't do it. Bugfix: don't trust the Tcl-accessible version of DSCR to flag whether RDTR needs to be restored when resuming.
* ARM11: streamline debug entryDavid Brownell2009-12-021-25/+20
| | | | | | | | | | | | | Streamline arm11_on_enter_debug_state() entry: - It should handle the standard updates: * target->debug_reason * target->state - Don't waste time re-reading DSCR; just pass it in Also rename the routine to "arm11_debug_entry()", matching the convention used elsewhere in OpenOCD.
* ARM11: remove arm11->targetDavid Brownell2009-12-021-9/+9
| | | | | Don't need/want arm11->target; we have arm11->arm.target instead. Also remove some unused watchpoint stuff.
* ARM DPM: tweak initializationDavid Brownell2009-12-021-4/+2
| | | | | | Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
* ARM: core DPM support for watchpointsDavid Brownell2009-12-011-27/+8
| | | | | | | | | | | | | | | | | | | | | This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove previous mcr()/mrc() methodsDavid Brownell2009-12-011-75/+0
| | | | | | We don't need this code, now that the DPM code handles it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: "mcr" and "mrc" are ARM-specificDavid Brownell2009-12-011-3/+10
| | | | | | | | | | | | | | Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: write_memory() avoids increment checkDavid Brownell2009-11-271-9/+19
| | | | | | | | | | | | When writing to a chip's "reset yourself" register, the ARM11 code was reporting a spurious failure. Just don't bother checking for correctly incremented pointers given single-unit writes ... it's a bit faster that way too. (Reads should likely do the same thing. For that matter, such checks are usually just a waste...) Shrink an overlong parameter name, and associated lines'o'code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-8/+7
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* arm11: use register_commands()Zachary T Welch2009-11-241-35/+62
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-7/+7
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* ARM11: remove old R0..R15/CPSR codeDavid Brownell2009-11-241-193/+72
| | | | | | | | | | | | | | | | This finishes the basic switchover to the new register code, for everything except the debug registers. (And maybe we shouldn't have a cache for *those* which works this way...) The context save/restore code now uses the new code, but it's in a slightly different sequence. That should be fine since the R0/PC/CPSR stuff is all that really matters (and if we can update those, we can update the rest). Now there's no longer a way any code can be confused about which copy of "r1" (etc) to use. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard run_algorithm()David Brownell2009-11-241-172/+5
| | | | | | | | | | | | | | | | | | | | As with single stepping, the previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue, in favor of the more thoroughly tested/capable "standard" code. Fixes a bug in the resume() implementation: it wasn't handling two of its arguments correctly, preventing the "flash erase_check" algorithm from working. (This code needs a *subsequent* update for correct register handling, though... removing the confusion about which "r2", for example, to use.) This should resolve some "FIXME" comments too, for Thumb and processor mode support. It also gets rid of a nasty exit() call; servers should only have *clean* shutdown paths. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard single step simulationDavid Brownell2009-11-241-97/+31
| | | | | | | | | | | | | | | | | | The previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue. This should resolve all the "FIXME -- handle Thumb single stepping" comments too, and properly handle the processor's mode. (Modulo the issue that this code doesn't yet handle two-byte breakpoints.) Clarify the comments about the the hardware single stepping. When we eventually share breakpoint code with Cortex-A8, we can just make that be the default on cores which support it. We may still want an override command, not just to facilitate testing but to cope with "instruction address mismatch" not quite being true single-step. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: partial support for standard ARM register interfaces.David Brownell2009-11-241-35/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This provides "standard" ARM register support -- with twenty or more shadow registers on top of what this code now handles, but properly associated with the various core modes -- parallel to the current register code. That is, the current code is stilil managing the "current" registers; the new code shadows them. You can see all the registers with "arm reg", modify the shadows like "r8_fiq" or "sp_abt" with "reg", and see them get properly written back when you step. (Just don't do that with any of the registers managed by the "old" code ...) It also switches to using more standard code, relying on those standard registers, in two places: (a) the poll status display, which now shows core state (ARM/Thumb/...) and mode (Supervisor, IRQ, etc); and (b) GDB register access. So it's not a full migration, there are warts -- every place that touches the old register cache is a potential bug -- but it's a small more-or-less-comprehensible step that's even somewhat useful. Later patches complete the migration. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove register "history" debug stuffDavid Brownell2009-11-241-50/+0
| | | | | | | | | | | | | | This was a private mechanism to snapshot registers before leaving debug state, and then on reentry to optionally display what changed. It was coupled to the private register cache, which won't be sticking around in that form for much longer. Remove (instead of teaching it how to handle *all* the registers). (The idea is interesting, but we ought to be able to implement this in a generic way. Ideally through Tcl scripts that can automatically be invoked following debug entry...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove unused state and exportsDavid Brownell2009-11-221-17/+18
| | | | | | | | | For now there's no point in saving this stuff after examine() checks it out as OK. Ditto exporting symbols that aren't used outside of the module which defines them. In fact, those two things needlessly complicate the code... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: macro cleanupDavid Brownell2009-11-221-56/+30
| | | | | | | | | | | | | | | | | Make this code look more like the rest of the OpenOCD code. - Use calloc() directly, not NEW() ... and fix some potential memory leaks while we're at it. - Remove FNC_INFO ... it's a NOP that just clutters things, and it's trivial for developers to add tracing as needed. - Replace FNC_INFO_NOTIMPLEMENTED with LOG_WARNING calls; ditto. And stop having those call sites wrongly succeed! - Waste less space with the CHECK_RETVAL() macro. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove needless string format #ifdefferyDavid Brownell2009-11-221-6/+15
| | | | | | | | We don't need to use size_t in these places; so it's easy to be rid of the need for this #ifdef and its MS-derived portability problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove disabled register hooksDavid Brownell2009-11-221-88/+1
| | | | | | | | Minor cleanup of ARM11 register handling: remove disabled register hooks. This should all be handled by shared code, and this stuff is just clutter. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add handle_command_parse_bool command helperZachary T Welch2009-11-181-45/+10
| | | | | | | | | Rewrite arm11_handle_bool to provide a generic on/off command helper. Refactors COMMAND_PARSE_BOOL to use new command_parse_bool helper, which gets reused by the new command_parse_bool_any helper. This later helper is called by the new command helper function to accepts any on/off, enable/disable, true/false, yes/no, or 0/1 parameter.
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-4/+17
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add is_arm_mode()David Brownell2009-11-171-1/+1
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-38/+3
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-2/+2
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-3/+3
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-8/+6
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove some more duplicate includesDavid Brownell2009-11-171-1/+0
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: fewer exit() callsDavid Brownell2009-11-161-4/+6
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: register (most) standard ARM commandsDavid Brownell2009-11-161-0/+2
| | | | | | | Have ARM11 register the "standard" ARM commands. For now, only disassembly really works. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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