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* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-3/+0
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-221-0/+8
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-11/+5
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: pass 'struct reg *' to register r/w routinesDavid Brownell2009-11-201-3/+3
| | | | | | | | | | | | | | | | Implementations need to access the register struct they modify; make it easier and less error-prone to identify the instance. (This removes over 10% of the ARMV4_5_CORE_REG_MODE nastiness...) Plus some minor fixes noted when making these updates: ARM7/ARM9 accessor methods should be static; don't leave CPSR wrongly marked "dirty"; note significant XScale omissions in register handling; and have armv4_5_build_reg_cache() record its result. Rename "struct armv4_5_core_reg" as "struct arm_reg"; it's used for more than those older architecture generations. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create/use register_cache_invalidate()David Brownell2009-11-191-2/+0
| | | | | | | | | | | | | | | Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove per-register mallocDavid Brownell2009-11-191-0/+1
| | | | | | | Just pre-allocate memory for the cached register value. Shrinks heap overhead; increases locality-of-reference. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-0/+1
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: setup "secure monitor mode" shadow regsDavid Brownell2009-11-181-2/+3
| | | | | | | | | | | | | Teach the "armv4_5" register code to understand about the secure monitor mode: - Add the other three shadowed registers to the arrays - Support another internal mode number (sigh) in mappings - Catch malloc/calloc failures building that register cache This should kick in for Cortex-A8 and ARM1176. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add "core_type" field to "struct arm"David Brownell2009-11-181-1/+9
| | | | | | | | | | It's used to flag cores with the "TrustZone" extension, and is used in subsequent patches to set up support for the registers shadowed by its new secure monitor mode. The ARM1176 and Cortex-A8 both support this new mode. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add is_arm_mode()David Brownell2009-11-171-3/+3
| | | | | | | | | | | | | | | | | | Add a new is_arm_mode() predicate, and use it to replace almost all calls to current armv4_5_mode_to_number(). Eventually those internal mode numbers should vanish... along with their siblings in the armv7a.c file. Remove a handful of superfluous checks ... e.g. the mode number was just initialized, or (debug entry methods) already validated. Move one of the macros using internal mode numbers into the only file which uses that macro. Make the tables manipulated with those numbers be read-only and, where possible, static so they're not confused with part of the generic ARM interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-2/+2
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-0/+2
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: don't include "log.h" from "armv4_5.h"David Brownell2009-11-161-1/+0
| | | | | | | No point in multiple includes, and that file doesn't use its functions any more. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: move mode functions out of headerDavid Brownell2009-11-161-38/+4
| | | | | | | | | They're really too big to inline, at least for code that's not in any performance-critical loops. Also move the associated string table to the rodata section. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "etm.h"David Brownell2009-11-161-1/+1
| | | | | | | Don't include it in more headers than necessary; just use it in the few files that actually need it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: no implicit #includes of "register.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | | | Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "command.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: memory utils aren't ARM7/ARM9 dependentDavid Brownell2009-11-151-3/+6
| | | | | | | | | | | | | | | | The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_context_t -> struct command_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-11/+11
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg.
* armv4_5_common_t -> struct armZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and just use struct arm.
* etm_context_t -> struct etm_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct etm_context.
* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* armv4_5_core_reg_t -> struct armv4_5_core_regZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_core_reg.
* armv4_5_algorithm_t -> struct armv4_5_algorithmZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv4_5_algorithm.
* reg_param_t -> struct reg_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg_param.
* mem_param_t -> struct mem_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct mem_param.
* ETM: remove old mid-level ETM handleDavid Brownell2009-11-111-0/+1
| | | | | | | | | | | | | | | | | | Now that nothing uses the old ETM handle any more, remove it. Add minimal header tweaks, letting non-ARM7 and non-ARM9 cores access ETM facilities. Now ARM11 could support standard ETM (and ETB) access as soon as it derives from "struct arm" ... its scanchain 6 is used access the ETM, just like ARM7 and ARM9. The Cortex parts (both M3 and A8) will need modified access methods (via ETM init parameters), so they use the DAP. Our first A8 target (OMAP3) needs that for both ETM and ETB, but the M3 ETM isn't very useful without SWO trace support (it's painfully stripped down), so that support won't be worth adding for a while. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: start generalized base typeDavid Brownell2009-11-111-5/+31
| | | | | | | | | | | | | | | | Rename "struct armv4_5_common_s" as "struct arm". It needs a bit more work to be properly generic, and to move out of this header, but it's the best start we have on that today. Add and initialize an optional ETM pointer, since that will be the first thing that gets generalized. The intent being: all ARMs should eventually derive from this "struct arm", so they can reuse the current ETM logic. (And later, more.) Currently the ARM cores that *don't* so derive are only ARMv7-M (and thus Cortex-M3) and ARM11. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* src/target: remove 'extern' and wrap headersZachary T Welch2009-11-091-7/+13
| | | | Remove extern keywords from function prototypes and wrap long lines.
* target: provide container_of()David Brownell2009-11-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Provide a cleaner way to handle single inheritance of targets in C, using the same model Linux does: structs containing other structs, un-nested via calls to a "container_of()" macro that are packaged in typesafe inline functions. Targets already use this containment idiom, but make it much more complicated because they un-nest using embedded "void *" pointers ... in chains of up to five per target, which is all pure needless complication. (Example: arm92x core, arm9tdmi, arm7_9, armv4_5 ... on top of the base "target" class.) Applying this scheme consistently simplifies things, and gets rid of many error-prone untyped pointers. It won't change any part of the type model though -- it just simplifies things. (And facilitates more cleanup later on.) Rule of thumb: where there's an X->arch_info void* pointer, access to that pointer can and should be removed. It may be convenient to set up pointers to some of the embedded structs; and shrink their current "*_common" names (annoyingly long). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* mcr/mrc interface work. Implemented for arm926ejs and arm720t. mcr/mrc ↵Øyvind Harboe2009-10-231-0/+18
| | | | commands added.
* portability updatesDavid Brownell2009-10-141-1/+1
| | | | | | | | | Based on some patches from <redirect.slash.nil@gmail.com> for preliminary Win64 compilation. More such updates are needed, but they need work. Compile tested on 64 and 32 bit Linuxes, and Cygwin. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* David Brownell <david-b@pacbell.net> oharboe2009-09-091-0/+1
| | | | | | | | | | | | | | | | | Optionally shave time off the armv4_5 run_algorithm() code: let them terminate using software breakpoints, avoiding roundtrips to manage hardware ones. Enable this by using BKPT to terminate execution instead of "branch to here" loops. Then pass zero as the exit address, except when running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores now set a flag saying they're ARMv4. Use that mechanism in arm_nandwrite(), for about 3% speedup on a DaVinci ARM926 core; not huge, but it helps. Some other algorithms could use this too (mostly flavors of flash operation). git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* more debug output for translation of arm mode number to enumoharboe2009-07-061-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2481 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* a bit more debug output for translation of invalid mode numbersoharboe2009-07-061-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2480 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '=' whitespacezwelch2009-06-231-4/+4
| | | | | | | | | - Replace ')\(=\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(=\)(' with '\1 \2 ('. - Replace '\(\w\)\(=\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2372 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u32' to 'uint32_t' in src/target/arm*zwelch2009-06-181-2/+2
| | | | | | | | - Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2278 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> whitespace fixes.oharboe2009-05-101-16/+16
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1690 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove redundant declarations to allow building with -Wredundant-decls.zwelch2009-04-291-1/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Zach Welch <zw@superlucidity.net> use ARM4_5_MODE_ANY instead of -1oharboe2009-04-191-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1474 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - remove target specific variant and use target->variant memberntfreak2008-12-131-1/+0
| | | | | | | - fix build warning in cortex_m3 - code cleanup - remove trailing lf and convert c++ comments git-svn-id: svn://svn.berlios.de/openocd/trunk@1238 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - added myself to copyright on files i remember adding large contributions ↵ntfreak2008-09-201-0/+3
| | | | | | | | | for over the years - cleaned up headers to match rest of code - added missing svn props for previously added files git-svn-id: svn://svn.berlios.de/openocd/trunk@987 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* fix mode output when illegal arm mode is detected. Now prints illegal mode ↵oharboe2008-05-191-1/+1
| | | | | | for index -1. git-svn-id: svn://svn.berlios.de/openocd/trunk@664 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* This matters for embedded devices, but is probably not observably better for ↵oharboe2008-05-071-2/+39
| | | | | | PC hosted OpenOCD. git-svn-id: svn://svn.berlios.de/openocd/trunk@647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fixed target->type->poll() return valueoharboe2008-02-241-1/+1
| | | | | | | | | | | - added arch_state to show status of currently selected target - simplified target->type->arch_state() api. - clean up telnet output a bit - fixed GDB output for arch_state - removed a couple of unecessary exit()'s - cleaned up error propagation a bit in a few places git-svn-id: svn://svn.berlios.de/openocd/trunk@332 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - split fileio handling into fileio part and image handlingdrath2007-05-291-4/+4
| | | | | | | | | | | - reworked etm/etb into a generic etm part with trace capture drivers (currently only etb supported) - added XScale debug handler binary to repository - added Thumb disassembling (thanks to Vincent Palatin for this patch) - added support for non-CFI compatible flashes to cfi driver (currently only SST39VFxxx devices supported) This checkin is experimental, not suitable for general use git-svn-id: svn://svn.berlios.de/openocd/trunk@155 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - merged XScale branch back into trunkdrath2007-03-281-0/+10
| | | | | | | | | - fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c - free working area and register stuff if str7x block write algorithm failed - check PC after exiting a target algorithm in armv4_5.c git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - add missing parentheses around macro parameters (thanks to Matthias Bauch ↵drath2007-02-031-23/+23
| | | | | | for noticing this bug and providing a fix) git-svn-id: svn://svn.berlios.de/openocd/trunk@130 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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