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* ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell2009-12-021-0/+3
| | | | | | | | | | | Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: stop using CP15 opsDavid Brownell2009-12-011-5/+36
| | | | | | | | | | | The ARMv7-A code uses read_cp15() to access fault registers. Instead, use DPM operations directly, passing in the relevant MRC instructions. This eliminates per-operation overhead (though it'll be hard to observe, this is uncommon) and helps eliminate read_cp15(). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove target_type register_command callbackZachary T Welch2009-11-241-5/+1
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* armv7a: use register_commands()Zachary T Welch2009-11-241-27/+48
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* use COMMAND_REGISTER macroZachary T Welch2009-11-241-6/+6
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-221-1/+1
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-221-2/+1
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core statesDavid Brownell2009-11-191-6/+1
| | | | | | | | | | | | | | | We don't want an ARMv7-specific core state enumeration just to add ThumbEE state. Update the generic stuff to handle that, and replace the V7-specific bits with it. For Cortex-A8: on debug entry, check both the T and J bits instead of just the T bit. When the J bit is set, set the right state and warn appropriately. (And while we're at it, move the generic arm struct to the front of the v7a structure, for somewhat better code generation.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: use standard ARM core_mode symbolsDavid Brownell2009-11-191-1/+1
| | | | | | | | | The only way ARMv7-A modes differ from ARMv4/ARMv5 flavors is that v7-A is allowed to include "Secure monitor" support. That's now handled by our standard top-level ARM code ... so phase out the stuff that's specific to ARMv7-A. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify ARMv7-A register handlingDavid Brownell2009-11-181-103/+5
| | | | | | | | | | | | | | | | | | | ARMv7-A doesn't need to duplicate all the standard ARM code for register handling. - Switch Cortex-A8 to use the standard register code - Remove duplicated infrastructure from ARMv7-A - Have ARMv7-A arch_state() show CPSR, like other ARMs Add comments to show where the Cortex-A8 isn't actually doing the right thing for register reads/writes, unless core happens to be in the right mode to start with. (Looks like maybe there may be generic confusion between saved/current PSR values in all the ARM code ...) Make related ARMv7-A and Cortex-A8 symbols properly static. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: add arm_mode_name()David Brownell2009-11-171-11/+1
| | | | | | | | | | | | | | | Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: only use one set of dummy FPA registersDavid Brownell2009-11-171-15/+0
| | | | | | | | | | | | | | | | All ARM cores need to provide obsolete FPA registers in their GDB register dumps. (Even though cores with floating point support now generally use some version of VFP...) Clean up that support a bit by sharing the same dummy registers, and removing the duplicate copies. Eventually we shouldn't need to export those dummies. (This makes the ARMv7-M support include the armv4_5 header, and cleans up related #includes, but doesn't yet use anything from there except those dummies.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch2009-11-171-6/+6
| | | | Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
* command_handler: change 'args' to CMD_ARGVZachary T Welch2009-11-171-1/+1
| | | | | This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
* command_handler: change to 'argc' to CMD_ARGCZachary T Welch2009-11-171-1/+1
| | | | | This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
* target: simplify register get/set opsDavid Brownell2009-11-171-1/+0
| | | | | | | | | | | No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7-A: no exit() callsDavid Brownell2009-11-161-3/+3
| | | | | | | Also, switch integrity check over to the correct magic number, and remove duplicate v4/v5 #define. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7A: use standard disassemblerDavid Brownell2009-11-161-83/+0
| | | | | | We no longer need v7A-specific code for this. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* #include "target.h" less wildlyDavid Brownell2009-11-161-1/+0
| | | | | | | | | Don't include "target.h" from more headers than necessary. This avoids needless interdependencies and duplicated include paths. Don't needlessly include it in source files, either. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: less implicit inclusion of "command.h"David Brownell2009-11-161-1/+0
| | | | | | | | | | Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove unused "bitfield" infrastructureDavid Brownell2009-11-131-21/+10
| | | | | | | | | | | | | | We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* command_t -> struct commandZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct command.
* command_context_t -> struct command_contextZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct command_context.
* target_t -> struct targetZachary T Welch2009-11-131-8/+8
| | | | Remove misleading typedef and redundant suffix from struct target.
* reg_t -> struct regZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg.
* arm_instruction_t -> struct arm_instructionZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct arm_instruction.
* bitfield_desc_t -> struct bitfield_descZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct bitfield_desc.
* armv7a_core_reg_t -> struct armv7a_core_regZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct armv7a_core_reg.
* armv7a_common_t -> struct armv7a_commonZachary T Welch2009-11-131-7/+7
| | | | Remove misleading typedef and redundant suffix from struct armv7a_common.
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct swjdp_common.
* arm_adi,armv7[am]: use COMMAND_HELPER for helpersZachary T Welch2009-11-131-4/+4
| | | | | Rewrites the dap_* command helpers to use the COMMAND_HELPER paradigm. Uses CALL_COMMAND_HELPER to hide inherited calling conventions.
* use COMMAND_HANDLER macro to define all commandsZachary T Welch2009-11-131-13/+6
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* Cortex-A8: use the new inheritance/nesting schemeDavid Brownell2009-11-051-18/+10
| | | | | | | Use target_to_armv7a() etc, replacing needless pointer traversals. Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Improve armv7a command argument parsing.Zachary T Welch2009-11-051-5/+12
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* Cleanup: nuke trailling whitespacesYauheni Kaliuta2009-10-131-3/+3
| | | | Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
* ARMv7A: Report fault status registers when in Abort statemlu2009-10-011-0/+23
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2789 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Updated mode string list.mlu2009-09-151-2/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2713 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Report correct core instruction state for ARMv/A targetsmlu2009-09-081-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2678 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-081-0/+86
| | | | | | | | Provide an "armv7a disassemble" command. Current omissions include VFP (except as coprocessor instructions), Neon, and various Thumb2 opcodes that are not available in ARMv7-M processors. git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - fix build warningsntfreak2009-08-251-1/+1
| | | | | | - add svn props to recently added files armv7a.[ch] git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a fileoharboe2009-08-251-0/+301
and seed it with DAP access support using the current ADIv5 code. (With tweaks and cleanup from Øyvind and Dave.) The ARMv7-AR architecture manual is not publicly available (even in subset form like the ARMv7-M spec), so it's hard to distinguish between the Cortex-A8 implementation and the ARMv7-A architecture. The register set presumably is architectural, and so it's stored here; it's like earlier ARMs, with small additions. Ditto the instruction set, though Thumb2 support is used (extending Thumb support from ARMv6 with more 32-bit instructions) and there's this ThumbEE thing too. There is a new "debug monitor" mode, not yet fully addressed here, to support debugging in environments (like motor control) where halting debug mode is inadvisable. git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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