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* reg_cache_t -> struct reg_cacheZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct reg_cache.
* armv7m_core_reg_t -> struct armv7m_core_regZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv7m_core_reg.
* armv7m_algorithm_t -> struct armv7m_algorithmZachary T Welch2009-11-131-2/+2
| | | | Remove misleading typedef and redundant suffix from struct armv7m_algorithm.
* armv7m_common_t -> struct armv7m_commonZachary T Welch2009-11-131-5/+5
| | | | Remove misleading typedef and redundant suffix from struct armv7m_common.
* swjdp_common_t -> struct swjdp_commonZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct swjdp_common.
* reg_param_t -> struct reg_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct reg_param.
* mem_param_t -> struct mem_paramZachary T Welch2009-11-131-1/+1
| | | | Remove misleading typedef and redundant suffix from struct mem_param.
* src/target: remove 'extern' and wrap headersZachary T Welch2009-11-091-13/+20
| | | | Remove extern keywords from function prototypes and wrap long lines.
* Cortex-M3: use the new inheritance/nesting schemeDavid Brownell2009-11-051-3/+0
| | | | | | | | | | | | Use new target_to_cm3() and target_to_armv7m() inlines, instead of a series of x->arch_info conversions. Remove arch_info, since nothing uses it. Also fix an omission: the Cortex-M3 commands didn't verify that they were operating on that kind of target. Add comment about the ARMv7M version of that omission. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: provide container_of()David Brownell2009-11-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Provide a cleaner way to handle single inheritance of targets in C, using the same model Linux does: structs containing other structs, un-nested via calls to a "container_of()" macro that are packaged in typesafe inline functions. Targets already use this containment idiom, but make it much more complicated because they un-nest using embedded "void *" pointers ... in chains of up to five per target, which is all pure needless complication. (Example: arm92x core, arm9tdmi, arm7_9, armv4_5 ... on top of the base "target" class.) Applying this scheme consistently simplifies things, and gets rid of many error-prone untyped pointers. It won't change any part of the type model though -- it just simplifies things. (And facilitates more cleanup later on.) Rule of thumb: where there's an X->arch_info void* pointer, access to that pointer can and should be removed. It may be convenient to set up pointers to some of the embedded structs; and shrink their current "*_common" names (annoyingly long). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARMv7M: add docs, remove exportsDavid Brownell2009-11-051-1/+1
| | | | | | | | | | | | Add Doxygen for the exported ARMv7-M interfaces. Make the non-exported stuff static. Remove functions and data which are now observably unused. Add comment about a small speedup that the run_algorithm() logic could use. Shrink a few too-long lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* debug interface: get rid of unused pre_debug fnØyvind Harboe2009-11-051-1/+0
| | | | | | Removing unused code makes it much less mysterius. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-4/+24
| | | | | | | | | | | | | | | | | | | | | | Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net>:ntfreak2009-07-211-10/+4
| | | | | | | | | Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, ↵zwelch2009-07-161-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | David Brownell <david-b@pacbell.net>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace at end of lines, step 1.zwelch2009-06-231-16/+16
| | | | | | | - Replace '\s*$' with ''. git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs before ')'.zwelch2009-06-231-2/+2
| | | | | | | - Replace '[ \t]*[)]' with ')'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2377 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove whitespace that occurs after '('.zwelch2009-06-231-1/+1
| | | | | | | - Replace '([ \t]*' with '('. git-svn-id: svn://svn.berlios.de/openocd/trunk@2376 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixes '<<' whitespacezwelch2009-06-231-4/+4
| | | | | | | | | - Replace ')\(<<\)\(\w\)' with ') \1 \2'. - Replace '\(\w\)\(<<\)(' with '\1 \2 ('. - Replace '\(\w\)\(<<\)\(\w\)' with '\1 \2 \3'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2370 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Transform 'u32' to 'uint32_t' in src/target/arm*zwelch2009-06-181-6/+6
| | | | | | | | - Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2278 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Audit and eliminate redundant #include directives in arm target files.zwelch2009-05-111-3/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1714 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove redundant declarations to allow building with -Wredundant-decls.zwelch2009-04-291-1/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@1560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Changed armv7m and cortexm3 to use nev arm_adi_v5 instead of cortex_swjdp.mlu2009-04-271-0/+3
| | | | | | Added support for accessport ROM table identification, dap command. git-svn-id: svn://svn.berlios.de/openocd/trunk@1536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - added myself to copyright on files i remember adding large contributions ↵ntfreak2008-09-201-0/+3
| | | | | | | | | for over the years - cleaned up headers to match rest of code - added missing svn props for previously added files git-svn-id: svn://svn.berlios.de/openocd/trunk@987 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - removed duplicate cortex_m3_register_commandsntfreak2008-06-161-2/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@709 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - moved flash erase_check target code to target.cntfreak2008-05-271-0/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@694 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - added ARMV7_GDB_HACKS define to armv7m.h, enabling all gdb hacks to be ↵ntfreak2008-04-261-0/+5
| | | | | | | | enabled/disabled for testing - added armv7m dummy cpsr register to stop gdb setting thumb bit git-svn-id: svn://svn.berlios.de/openocd/trunk@623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - single core context used, removed debug context as thought unnecessary.ntfreak2008-04-101-24/+5
| | | | | | | | | - DCRDR now used to access special core registers - info is currently omitted from the cortex_m3 TRM ARM have told me this is the preferred access method and the docs will be updated soon. - now checks for User Thread Mode and Thread mode when halted. - removed repeated function declarations from command.c - cortex_m3_prepare_reset_halt removed, updated cortex_m3_assert_reset to suit git-svn-id: svn://svn.berlios.de/openocd/trunk@558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - 16 and 32 bit unaligned accesses supportedntfreak2008-03-111-31/+2
| | | | | | | | - uses packed transfers for 8/16bit read/writes greater than 4bytes - 8/16bit transfers now use address auto increment git-svn-id: svn://svn.berlios.de/openocd/trunk@495 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Uwe Hermann tightned up comments, etc. to follow OpenOCD policyoharboe2008-03-021-3/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@431 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Uwe Hermann: oharboe2008-02-291-0/+1
| | | | | | | Small cosmetic fixes in the license header to make them all look the same, fix some typos, update README. git-svn-id: svn://svn.berlios.de/openocd/trunk@396 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Bruck spotted an omission in svn 322oharboe2008-02-251-1/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@336 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - add verify_image commandntfreak2007-10-221-0/+2
| | | | | | - add support for gdb qCRC packet (compare-sections command) git-svn-id: svn://svn.berlios.de/openocd/trunk@210 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - Fixed display of sector sizes in flash.cmlu2007-09-101-0/+1
| | | | | | | | | - Clean up, remove unused variables and code in armv7, cortex_m3 and stellaris code - Move restore_context from cortex_m3 to armv7m - Updated halt handling for cortex_m3 git-svn-id: svn://svn.berlios.de/openocd/trunk@206 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - ST STM32x cortex support addedntfreak2007-06-241-7/+8
| | | | | | | | - ST STM32x flash support added - cleaned up armv7m and cortex-m3 support, removed luminary specific code - cortex-m3 16bit read/write added (required for STM32x flash programming) git-svn-id: svn://svn.berlios.de/openocd/trunk@177 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* - merged support for Cortex-M3 from cortex-m3 branch (thanks to Magnus Lundin)drath2007-06-141-0/+248
git-svn-id: svn://svn.berlios.de/openocd/trunk@170 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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