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* explode tcl_target_func into many handlersZachary T Welch2009-11-281-387/+521
| | | | | | | | Eliminate the monolithic tcl_target_func by registering each of its commands using the new chained command registration mechanism. Also chains the target's commands under the CPU command, though these may not work properly without some further modification.
* split jim_target into multiple handlersZachary T Welch2009-11-281-109/+137
| | | | | | | | The 'target' command group was implemented using its own command dispatching, which can be eliminated by using the new chained command registration mechanism. This patch splits the jim_target() function into individual handlers, which makes them to be visible to the help and usage commands. These one-trick handlers are much easier to understand.
* ARM11: fix warning on amd64David Brownell2009-11-281-1/+4
| | | | | | Previous version of JTAG_DEBUG() macro hid this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: fix dbgtap JTAG_DEBUGDavid Brownell2009-11-281-2/+2
| | | | | | | There is no DEBUG() macro; don't call one! Always at least *parse* debug code, to help prevent such errors. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: uplevel add_{break,watch}point() error checksDavid Brownell2009-11-286-38/+23
| | | | | | | | | | | | | | | | | | | | | | | | In target_type.h it's documented that the target must be halted for add_breakpoint() ... and with slight ambiguity, also for its add_watchpoint() sibling. So rather than verifying that constraint in the CPU drivers, do it in the target_add_{break,watch}point() routines. Add minor paranoia on the remove_*point() paths too: save the return value, and print it out in in the LOG_DEBUG message in case it's nonzero. Note that with some current cores, like all ARMv7 ones I've looked at, there's no technical issue preventing watchpoint or breakpoint add/remove operations on active cores. This model seems deeply wired into OpenOCD though. ALSO: the ARM targets were fairly "good" about enforcing that constraint themselves. The MIPS ones were relied on other code to catch such stuff, but it's not clear such code existed ... keep an eye out for new issues on MIPS. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: remove unused TARGET_EVENT_OLD_* symbolsDavid Brownell2009-11-281-2/+0
| | | | | | Just two *_OLD_* symbols left... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: support "reset-assert" eventDavid Brownell2009-11-271-5/+28
| | | | | | | | | | | | | | Use the new "reset-assert" event; else SRST; else fail. Tested on an OMAP3, using the event. NOTE: still doesn't handle "reset halt". For some reason neither VCR nor PRCR seemed effective; they held the value that was written, but VCR didn't trigger debug entry when the reset vector fired (maybe the vector needs configuring?) and PRCR refused to hold the chip in reset until deassert() could force the core into debug state. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: groundwork for "reset-assert" eventDavid Brownell2009-11-272-3/+21
| | | | | | | | | This defines a "reset-assert" event and a supporting utility routine, and documents both how targets should implement it and how config scripts should use it. Core-specific updates are needed to make this work. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: write_memory() avoids increment checkDavid Brownell2009-11-271-9/+19
| | | | | | | | | | | | When writing to a chip's "reset yourself" register, the ARM11 code was reporting a spurious failure. Just don't bother checking for correctly incremented pointers given single-unit writes ... it's a bit faster that way too. (Reads should likely do the same thing. For that matter, such checks are usually just a waste...) Shrink an overlong parameter name, and associated lines'o'code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* XScale: add stub {read,write}_phys routinesDavid Brownell2009-11-261-0/+20
| | | | | | | | | Just make these fail, instead of letting them write over potentially random memory. Users should be able to work around the lack of real implementations by disbling the MMU by hand ... until someone provides a Real Fix. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: create and use target_name()David Brownell2009-11-254-19/+29
| | | | | | | | | | | | | Several of the sites now using target_type_name() really ought to be using an instance-specific name. Create a function called target_name(), accessing the instance's own (command) name. Use it in several places that really should be displaying instance-specific names. Also in several places which were already doing so, but which had no wrapper to call. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: target_get_name() --> target_type_name()David Brownell2009-11-256-15/+24
| | | | | | | | | | | | | There are two names that may matter on a per-target basis. One is a per-instance name (for example, "at91sam7s.cpu"). The other is the name of its type (for example, "arm7tdmi"), which is shared among multiple targets. Currently target_get_name() returns the type name, which is misleading and is rarely appropriate for target diagnostics. Rename that as target_type_name(). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: minor armv4/armv5 cleanupDavid Brownell2009-11-251-1/+12
| | | | | | Lines of 300+ characters are still bad; debug tweaks. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: comment tweaks in ADIv5David Brownell2009-11-251-2/+5
| | | | | | "OptimoDE DESS" is ARM's semicustom DSPish stuff. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM7/9: shrink run_algorithm_inner() linesDavid Brownell2009-11-251-2/+10
| | | | | | 300+ characters is unreasonable. So is half that. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* use ARRAY_SIZE macroZachary T Welch2009-11-255-24/+24
| | | | | Search and destroy lingering cases where the ARRAY_SIZE macro should be used to convey more intrinsic meaning in the OpenOCD code.
* add 'testee' target typeZachary T Welch2009-11-253-1/+52
| | | | | | | Alliteration aside, this should provide the final piece of the puzzle for developers that want to get started writing a new target type. In this way, it also seeks to complement the 'dummy' interface driver and 'faux' NOR flash driver.
* add jim_handler to command_registrationZachary T Welch2009-11-241-23/+45
| | | | | | Adding jim_handler field to command_registration allows removing the register_jim helper. All command registrations now go through the register_command{,s}() functions.
* remove register_commands from etm_capture_driverZachary T Welch2009-11-245-31/+17
| | | | | | Converts callback to an array of command_registration records. Moves oocd_trace driver definition to end of file to eliminate useless forward declaration.
* remove target_type register_command callbackZachary T Welch2009-11-2431-149/+89
| | | | | | Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
* xscale: use register_commands()Zachary T Welch2009-11-241-23/+107
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* trace: use register_commands()Zachary T Welch2009-11-241-10/+29
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* target_request: use register_commands()Zachary T Welch2009-11-241-8/+21
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* target: use register_commands()Zachary T Welch2009-11-241-104/+201
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* oocd_trace: use register_commands()Zachary T Welch2009-11-241-10/+32
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* etm_dummy: use register_commands()Zachary T Welch2009-11-241-7/+20
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* etm: use register_commands()Zachary T Welch2009-11-241-37/+89
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* etb: use register_commands()Zachary T Welch2009-11-241-8/+20
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* cortex_m3: use register_commands()Zachary T Welch2009-11-241-19/+36
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* cortex_a8: use register_commands()Zachary T Welch2009-11-241-17/+25
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* armv7m: use register_commands()Zachary T Welch2009-11-241-28/+48
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* armv7a: use register_commands()Zachary T Welch2009-11-241-27/+48
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* armv4_5: use register_commands()Zachary T Welch2009-11-241-18/+34
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* arm9tdmi: use register_commands()Zachary T Welch2009-11-241-12/+21
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* arm966e: use register_commands()Zachary T Welch2009-11-241-12/+23
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* arm926ejs: use register_commands()Zachary T Welch2009-11-241-14/+22
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* arm920t: use register_commands()Zachary T Welch2009-11-241-27/+47
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* arm7_9_common: use register_commands()Zachary T Welch2009-11-241-20/+37
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* arm720t: use register_commands()Zachary T Welch2009-11-241-15/+23
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* arm11: use register_commands()Zachary T Welch2009-11-241-35/+62
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* use COMMAND_REGISTER macroZachary T Welch2009-11-2420-114/+114
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* improve startup tcl scriptsZachary T Welch2009-11-241-15/+3
| | | | | Fix a couple of layering violations missed in the last round. Add missing comment headers.
* Cortex-A8: avoid DSCR readsDavid Brownell2009-11-241-48/+103
| | | | | | | | | | | | | | | | | There was a lot of needless handshaking overhead in the current Cortex-A8 DCC/ITR operations, since the status read by each step was discarded rather than letting the next step know it. This shrinks the handshaking by: (a) passing status along from previous steps, avoiding re-fetching; which enables the big win (b) relying on a useful invariant: that the DSCR_INSTR_COMP bit is set after every call to a DPM method. A "reg sp_usr" call previously took 17 flushes; now it takes just 9. This visibly speeds common operations like entry to debug state and stepping, as well as "arm reg" and so on. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: hook up DPMDavid Brownell2009-11-241-323/+35
| | | | | | | | | This replaces two versions of register access functions. One was commented out, and seemed to have uncertain intent. The other was fairly new, and helped motivate the DPM framework once I observed that the ARM11 was doing the very same ops. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: implement DPMDavid Brownell2009-11-244-9/+176
| | | | | | | | This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: minor cleanupDavid Brownell2009-11-242-26/+35
| | | | | | | | Make various functions static, add some comments, report vector catch as a flavor of DBG_REASON_BREAKPOINT, get rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old R0..R15/CPSR codeDavid Brownell2009-11-242-196/+74
| | | | | | | | | | | | | | | | This finishes the basic switchover to the new register code, for everything except the debug registers. (And maybe we shouldn't have a cache for *those* which works this way...) The context save/restore code now uses the new code, but it's in a slightly different sequence. That should be fine since the R0/PC/CPSR stuff is all that really matters (and if we can update those, we can update the rest). Now there's no longer a way any code can be confused about which copy of "r1" (etc) to use. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard run_algorithm()David Brownell2009-11-241-172/+5
| | | | | | | | | | | | | | | | | | | | As with single stepping, the previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue, in favor of the more thoroughly tested/capable "standard" code. Fixes a bug in the resume() implementation: it wasn't handling two of its arguments correctly, preventing the "flash erase_check" algorithm from working. (This code needs a *subsequent* update for correct register handling, though... removing the confusion about which "r2", for example, to use.) This should resolve some "FIXME" comments too, for Thumb and processor mode support. It also gets rid of a nasty exit() call; servers should only have *clean* shutdown paths. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard single step simulationDavid Brownell2009-11-241-97/+31
| | | | | | | | | | | | | | | | | | The previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue. This should resolve all the "FIXME -- handle Thumb single stepping" comments too, and properly handle the processor's mode. (Modulo the issue that this code doesn't yet handle two-byte breakpoints.) Clarify the comments about the the hardware single stepping. When we eventually share breakpoint code with Cortex-A8, we can just make that be the default on cores which support it. We may still want an override command, not just to facilitate testing but to cope with "instruction address mismatch" not quite being true single-step. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: partial support for standard ARM register interfaces.David Brownell2009-11-241-35/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This provides "standard" ARM register support -- with twenty or more shadow registers on top of what this code now handles, but properly associated with the various core modes -- parallel to the current register code. That is, the current code is stilil managing the "current" registers; the new code shadows them. You can see all the registers with "arm reg", modify the shadows like "r8_fiq" or "sp_abt" with "reg", and see them get properly written back when you step. (Just don't do that with any of the registers managed by the "old" code ...) It also switches to using more standard code, relying on those standard registers, in two places: (a) the poll status display, which now shows core state (ARM/Thumb/...) and mode (Supervisor, IRQ, etc); and (b) GDB register access. So it's not a full migration, there are warts -- every place that touches the old register cache is a potential bug -- but it's a small more-or-less-comprehensible step that's even somewhat useful. Later patches complete the migration. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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