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* ARM: fix single-step of Thumb unconditional branchNicolas Pitre2009-10-271-2/+2
| | | | | | | | | Only type 1 branch instruction has a condition code, not type 2. Currently they're both tagged with ARM_B which doesn't allow for the distinction. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix target address when disassembling Thumb BLXNicolas Pitre2009-10-271-0/+1
| | | | | | | | A Thumb BLX instruction is branching to ARM code, and therefore the first 2 bits of the target address must be cleared. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: fix Thumb mode handling when single-stepping register based branch insnsNicolas Pitre2009-10-261-22/+33
| | | | | | | | | | | | | | | | | | | Currently, OpenOCD is always caching the PC value without the T bit. This means that assignment to the PC register must clear that bit and set the processor state to Thumb when it is set. And when the PC register value is transferred to another register or stored into memory then the T bit must be restored. Discussion: It is arguable if OpenOCd should have preserved the original PC value which would have greatly simplified this code. The processor state could then be obtained simply by getting at bit 0 of the PC. This however would require special handling elsewhere instead since the T bit is not always relevant (like when PC is used with ALU insns or as an index with some addressing modes). It is unclear which way would be simpler in the end. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: allow proper single stepping of Thumb BL and BLX instructionsNicolas Pitre2009-10-261-0/+12
| | | | | | | | | | | | | | Whenever an unconditional branch with the H bits set to 0b10 is met, the offset must be combined with the offset from the following opcode and not ignored like it is now. A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder would be a simpler solution. That might be true when single-stepping of Thumb2 code is implemented. But for now this appears to be the simplest solution to fix Thumb1 support. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: call thumb_pass_branch_condition() only for actual branch opcodesNicolas Pitre2009-10-261-8/+6
| | | | | | | | | | | | | | Calling it first with every opcodes and then testing if the opcode was indeed a branch instruction is wasteful and rather strange. If ever thumb_pass_branch_condition() has side effects (say, like printing a debugging traces) then the result would be garbage for most Thumb instructions which have no condition code. While at it, let's make the nearby code more readable by reducing some of the redundant brace noise and reworking the error handling construct. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM ADIv5: "dap info" gets more readableDavid Brownell2009-10-261-33/+268
| | | | | | | | | | | | | | Make the "dap info" output more comprehensible: - Don't show CIDs unless they're incorrect (only four bits matter) - For CoreSight parts, interpret the part type - Interpret the part number - Show all five PID bytes together - Other minor cleanups Also some whitespace fixes, and shrink a few overlong source lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* check if mmu is enabled before using mmu code pathØyvind Harboe2009-10-251-1/+1
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* ARM: rename "arm9tdmi vector_catch" to "arm9 ..."David Brownell2009-10-251-5/+3
| | | | | | And update doc accordingly. That EmbeddedICE register was introduced for ARM9TDMI and then carried forward into most new chips that use EmbeddedICE.
* xscale: always reload handler after resetDavid Brownell2009-10-252-19/+11
| | | | | | | | | | | | | | | | | | | | Remove needless debug handler state. - "handler_installed" became wrong as soon as the second TRST+SRST reset was issued ... so the handler was never reloaded after the reset removed it from the mini-icache. This fixes the bug where subsequent resets fail on PXA255 (if the first one even worked, which is uncommon). Other XScale chips would have problems too; PXA270 seems to have, IXP425 maybe not. - "handler_running" was never tested; it's pointless. Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset. It was no more valid than the XScale's mini-icache. (Though ... such invalidations might be better done in "SRST asserted" callbacks.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm9tdmi vector_catch: reserved means "don't use"David Brownell2009-10-232-3/+2
| | | | | | | Bit 5 shouldn't be used. Remove all support for modifying it. Matches the exception vector table, of course ... more than one bootloader uses that non-vector to help distinguish valid boot images from random garbage in flash.
* Improve help for arm9 vector_catch.Øyvind Harboe2009-10-231-1/+3
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* Remove debug output that could cause compile warnings.Øyvind Harboe2009-10-231-2/+0
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* mcr/mrc interface work. Implemented for arm926ejs and arm720t. mcr/mrc ↵Øyvind Harboe2009-10-236-12/+241
| | | | commands added.
* Embedded ICE version is now dumped with debug_level 1Øyvind Harboe2009-10-231-2/+2
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* Ferocion: fix corruption of r0 when resuming Thumb modeNicolas Pitre2009-10-221-2/+1
| | | | | | | | The wrong variable (pc instead of r0) was used. Furthermore, someone did cover this error by stupidly silencing the compiler warning that occurred before a dummy void reference to r0 was added to the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* have "reg" command print cache names tooDavid Brownell2009-10-221-0/+2
| | | | | | | When dumping over 100 registers (as on most ARM9 + ETM cores), aid readability by splitting them into logical groups. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ETM: rename registers, doc tweaksDavid Brownell2009-10-221-47/+54
| | | | | | | | | | | | | | | The register names are perversely not documented as zero-indexed, so rename them to match that convention. Also switch to lowercase suffixes and infix numbering, matching ETB and EmbeddedICE usage. Update docs to be a bit more accurate, especially regarding what the "trigger" event can cause; and to split the issues into a few more paragraphs, for clarity. Make "configure" helptext point out that "oocd_trace" is prototype hardware, not anything "real". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* retire obsolete mXY_phys commands. Handled by generic memory read/modify ↵Øyvind Harboe2009-10-215-341/+0
| | | | commands and target read/write physical memory callbacks.
* read/write physical target fn'sØyvind Harboe2009-10-212-0/+53
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* add support for target_read/write_phys_memory callbacks.Øyvind Harboe2009-10-211-2/+27
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* Added target_read/write_phys_memory() fn's. mdX/mwX commands updated to ↵Øyvind Harboe2009-10-212-10/+84
| | | | support phys flag to specify bypassing of MMU.
* Retire obsolete and superfluous implementations of virt2phys in each target. ↵Øyvind Harboe2009-10-214-129/+0
| | | | This is done in a polymorphic implementation in target.c
* First cut at implementing software breakpoints for mmu read only memoryØyvind Harboe2009-10-211-2/+37
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* Defined target_write_memory() to be able to handle implementing breakpoints ↵Øyvind Harboe2009-10-211-0/+24
| | | | for read only ram(e.g. MMU write protected.
* Improve Makefile rules for XScale debug handler; fixes 'make distcheck'.Zachary T Welch2009-10-191-5/+8
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* fix single step of bx instruction going into Thumb modeNicolas Pitre2009-10-191-1/+1
| | | | | | | | Without this fix, the following code cannot be single stepped: add ip, pc, #1 bx ip [thumb code here]
* More MinGW C99 printf complianceRedirect 'Slash' NIL2009-10-171-1/+2
| | | | | | | | Passing "--std=gun99" is unfortunately not sufficient to make current MinGW compilers conform with respect to checking printf format strings. (The C runtime seems not to have problems.) Fix by using a "gnu_printf" format specifier not "printf".
* build tweak for bin2charDavid Brownell2009-10-171-3/+4
| | | | | | Work better when building outside the source tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* xscale: better fix for debug_handler.binDavid Brownell2009-10-164-26/+20
| | | | | | | | | | | | | Generate a C struct with the data, and use that, instead of an assembly language file. The assembly language causes issues on Darwin and MS-Windows, which don't necessarily use GNU AS; or if they do, don't necessarily use its ELF syntax. It's also better in two other ways: fewer global symbols; and the init-time size check gets optimized away at compile time. (Unless it fails, in which case bigger chunks of the file vanish.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* portability updatesDavid Brownell2009-10-142-3/+3
| | | | | | | | | Based on some patches from <redirect.slash.nil@gmail.com> for preliminary Win64 compilation. More such updates are needed, but they need work. Compile tested on 64 and 32 bit Linuxes, and Cygwin. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Work in progress on arm11 reset. Assert srst.Øyvind Harboe2009-10-141-6/+50
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* Fix problems building xscale_debug.SDavid Brownell2009-10-141-0/+6
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* fix detection of PLD instructionsLennert Buytenhek2009-10-131-1/+1
| | | | | Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix pass_condition() LE condition code checkLennert Buytenhek2009-10-131-3/+3
| | | | | | | | The LE check is obviously buggy (as easily triggered during some testing), but I didn't audit the rest of the cases. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cleanup: nuke trailling whitespacesYauheni Kaliuta2009-10-133-14/+14
| | | | Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
* Do not replace virt2phys with the default one if it was assignedYauheni Kaliuta2009-10-131-1/+0
| | | | Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
* Fix warning.Øyvind Harboe2009-10-131-1/+1
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* Delete commented out code. Add a bit of error checking.Øyvind Harboe2009-10-132-45/+20
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* Propagate error from assert, deassert and halt on tcl target object.Øyvind Harboe2009-10-131-5/+9
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* xscale: stackframe corruption bugfixDavid Brownell2009-10-131-36/+18
| | | | | | | | | | | Resolve a "FIX" comment; yes that was superfluous given that the JTAG core does that check by default. It was also buggy since it wrote to a stack frame that went away before the write happened!! Other fixes: remove pointless malloc(); zero-init scan_field_t values wherever they appear; whitespace scrub; spelling fix. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* More error propagation fixes.Øyvind Harboe2009-10-122-5/+8
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* arm11 burst writes are now only enabled for writes larger than 1 word. ↵Øyvind Harboe2009-10-121-2/+11
| | | | Single word writes are frequently used from reset init scripts to non-memory peripherals.
* Retire arm11 no_increment. Intended for future expansion to read/write to ↵Øyvind Harboe2009-10-121-8/+22
| | | | ports. New arm11 commands would have to be added to exploit it.
* Propagate wDTR/rDTR failure immediately, otherwise it's followed up by ↵Øyvind Harboe2009-10-121-0/+1
| | | | timeout errors.
* Fix warning and improve error message upon burst transfer failureØyvind Harboe2009-10-121-3/+3
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* Fix bogus 'transfer errors' with arm11 'memwrite burst enable'. A regression ↵Øyvind Harboe2009-10-121-5/+5
| | | | introduced in b8103660fa36a77158bd77379572c09913d85c00
* simplify XScale debug handler installationDavid Brownell2009-10-124-42/+58
| | | | | | | | | | | | | | | | | | | Load the XScale debug handler from the read-only data section instead of from a separate file that can get lost or garbaged. This eliminates installation and versioning issues, and also speeds up reset handling a bit. Plus some minor bits of cleanup related to loading that handler: comments about just what this handler does, and check fault codes while writing it into the mini-icache. The only behavioral changes should be cleaner failure modes after errors during handler loading, and being a bit faster. NOTE: presumes GNU assembly syntax, with ".incbin"; and ELF, because of the syntax of the ".size" directive. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* more xscale cleanup (mostly removing JTAG hooks)David Brownell2009-10-122-88/+65
| | | | | | | | | | | | | | | | Streamline/shrink some needless JTAG stuff: - Use #defines for the JTAG instructions; they can't ever change - Remove an unused (!) shadow of tap->ir_length - Stop using a copy of target->tap - Don't bother saving the variant after sanity checking ir_length Also, make target_create() work as on other targets: build the register cache later, making init_target() no longer be a NOP. Handle malloc failure; remove a comment that was obsoleted by the not-so-new target syntax. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Merge commit 'origin/master'Øyvind Harboe2009-10-123-256/+257
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| * xscale_load_ic cleanupDavid Brownell2009-10-111-16/+16
| | | | | | | | | | | | | | | | Remove unused and deprecated (in the arch spec) mode for loading code into the *main* icache (vs the "mini" icache). Disable some extremely noisy (and rarely useful) low-level debug messages Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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