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* add struct command_registrationZachary T Welch2009-11-242-23/+45
| | | | | | | | | Add a structure to encapsulate command registration information, rather than passing them all as parameters. Enables further API changes that require additional required or optional parameters. Updates the register_command API and COMMAND_REGISTER macro to use it, along with their documentation.
* use COMMAND_REGISTER macroZachary T Welch2009-11-2463-310/+286
| | | | | Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
* add COMMAND_REGISTER macroZachary T Welch2009-11-241-0/+4
| | | | | | | | Provides a migration path for the widely used register_command API, which needs to be updated to provide new functionality. This macro allows the API to change without having to update all of its callers at the same time.
* improve startup tcl scriptsZachary T Welch2009-11-244-19/+20
| | | | | Fix a couple of layering violations missed in the last round. Add missing comment headers.
* Cortex-A8: avoid DSCR readsDavid Brownell2009-11-241-48/+103
| | | | | | | | | | | | | | | | | There was a lot of needless handshaking overhead in the current Cortex-A8 DCC/ITR operations, since the status read by each step was discarded rather than letting the next step know it. This shrinks the handshaking by: (a) passing status along from previous steps, avoiding re-fetching; which enables the big win (b) relying on a useful invariant: that the DSCR_INSTR_COMP bit is set after every call to a DPM method. A "reg sp_usr" call previously took 17 flushes; now it takes just 9. This visibly speeds common operations like entry to debug state and stepping, as well as "arm reg" and so on. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: hook up DPMDavid Brownell2009-11-241-323/+35
| | | | | | | | | This replaces two versions of register access functions. One was commented out, and seemed to have uncertain intent. The other was fairly new, and helped motivate the DPM framework once I observed that the ARM11 was doing the very same ops. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: implement DPMDavid Brownell2009-11-244-9/+176
| | | | | | | | This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Cortex-A8: minor cleanupDavid Brownell2009-11-242-26/+35
| | | | | | | | Make various functions static, add some comments, report vector catch as a flavor of DBG_REASON_BREAKPOINT, get rid of needless/undesirable ARMV4_5_CORE_REG_MODE, etc. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* improve alloc_vprintfAndreas Fritiofson2009-11-241-27/+16
| | | | | | | | | | | | | | The previous implementation was unnecessarily complex. Get rid of the loops, let vsnprintf() tell us directly how much storage we need and allocate that. A second pass writes the actual string. Also add a va_end() that was missing. This should be much faster for large strings and less wasteful for small ones. A quirk that has been retained is that some callers patch in a newline at the end of the returned string and depend on alloc_vprintf to allocate at least one byte extra. Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: Zachary T Welch <zw@superlucidity.net>
* jlink: rewrite to use jtag_usb_openZachary T Welch2009-11-241-61/+15
| | | | Rewrite jlink_usb_open to use jtag_usb_open helper.
* jlink: remove superfluous indentationZachary T Welch2009-11-241-52/+55
| | | | | Rewrite logic to remove indentation in jlink_usb_open, in prep for further surgery.
* rlink: use jtag_usb_open helperZachary T Welch2009-11-241-82/+49
| | | | | | | Rewrite rlink_init routine to use jtag_usb_open helper. Eliminates some spurious calls to exit(). Wraps a tremendously long line of comment to fit 80 columns too.
* rlink: eliminate spurious indentationZachary T Welch2009-11-241-55/+54
| | | | Rework rlink_init to use less indentation. Best viewed with diff -w.
* vsllink: rewrite to use jtag_usb_openZachary T Welch2009-11-241-54/+30
| | | | | | Rewrite vsllink_usb_open to use jtag_usb_open helper. Eliminates spurious calls to exit().
* usbprog: use jtag_usb_openZachary T Welch2009-11-241-30/+13
| | | | Rewrite usbprob_jtag_open to use jtag_usb_open helper.
* arm-jtag-ew: use jtag_usb_openZachary T Welch2009-11-241-36/+17
| | | | Rewrite armjtagwe_usb_open to use jtag_usb_open.
* add jtag/usb_common.[ch] filesZachary T Welch2009-11-243-1/+97
| | | | | | | | Begins to consolidate code used by several USB JTAG interfaces. This first patch provides the required build system changes and a common jtag_usb_open routine, which will replace the guts for probing the busses and devices for possible VID/PID matches. The following patches convert each driver to use it.
* ARM11: remove old R0..R15/CPSR codeDavid Brownell2009-11-242-196/+74
| | | | | | | | | | | | | | | | This finishes the basic switchover to the new register code, for everything except the debug registers. (And maybe we shouldn't have a cache for *those* which works this way...) The context save/restore code now uses the new code, but it's in a slightly different sequence. That should be fine since the R0/PC/CPSR stuff is all that really matters (and if we can update those, we can update the rest). Now there's no longer a way any code can be confused about which copy of "r1" (etc) to use. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard run_algorithm()David Brownell2009-11-241-172/+5
| | | | | | | | | | | | | | | | | | | | As with single stepping, the previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue, in favor of the more thoroughly tested/capable "standard" code. Fixes a bug in the resume() implementation: it wasn't handling two of its arguments correctly, preventing the "flash erase_check" algorithm from working. (This code needs a *subsequent* update for correct register handling, though... removing the confusion about which "r2", for example, to use.) This should resolve some "FIXME" comments too, for Thumb and processor mode support. It also gets rid of a nasty exit() call; servers should only have *clean* shutdown paths. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: use standard single step simulationDavid Brownell2009-11-241-97/+31
| | | | | | | | | | | | | | | | | | The previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue. This should resolve all the "FIXME -- handle Thumb single stepping" comments too, and properly handle the processor's mode. (Modulo the issue that this code doesn't yet handle two-byte breakpoints.) Clarify the comments about the the hardware single stepping. When we eventually share breakpoint code with Cortex-A8, we can just make that be the default on cores which support it. We may still want an override command, not just to facilitate testing but to cope with "instruction address mismatch" not quite being true single-step. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: partial support for standard ARM register interfaces.David Brownell2009-11-241-35/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This provides "standard" ARM register support -- with twenty or more shadow registers on top of what this code now handles, but properly associated with the various core modes -- parallel to the current register code. That is, the current code is stilil managing the "current" registers; the new code shadows them. You can see all the registers with "arm reg", modify the shadows like "r8_fiq" or "sp_abt" with "reg", and see them get properly written back when you step. (Just don't do that with any of the registers managed by the "old" code ...) It also switches to using more standard code, relying on those standard registers, in two places: (a) the poll status display, which now shows core state (ARM/Thumb/...) and mode (Supervisor, IRQ, etc); and (b) GDB register access. So it's not a full migration, there are warts -- every place that touches the old register cache is a potential bug -- but it's a small more-or-less-comprehensible step that's even somewhat useful. Later patches complete the migration. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove register "history" debug stuffDavid Brownell2009-11-242-59/+0
| | | | | | | | | | | | | | This was a private mechanism to snapshot registers before leaving debug state, and then on reentry to optionally display what changed. It was coupled to the private register cache, which won't be sticking around in that form for much longer. Remove (instead of teaching it how to handle *all* the registers). (The idea is interesting, but we ought to be able to implement this in a generic way. Ideally through Tcl scripts that can automatically be invoked following debug entry...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: implement provider for new DPM interfaceDavid Brownell2009-11-243-0/+80
| | | | | | | This is a very thin layer over some of the current ARM11 debug TAP utilities. The layer isn't yet hooked up. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: new DPM interfaceDavid Brownell2009-11-245-0/+625
| | | | | | | | | | | | | | | | | | | First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: cope with *any* error setting a breakpointDavid Brownell2009-11-241-26/+24
| | | | | | It's wrong to map unrecognized failure codes to success. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* support for scripts in $HOME/.openocdAndreas Fritiofson2009-11-241-1/+16
| | | | | | | | | | | | | Add $HOME/.openocd as the first default script search directory, allowing the user to override the standard scripts. Update the user guide with information on where OpenOCD expects to find configuration files and scripts. Also fixed some minor formatting issues. Add entry to NEWS as well. Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: fix gaffe when removing dynamic array allocationJerry Ling2009-11-241-3/+3
| | | | | | Classic sizeof() gaffe. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm926ejs: retire cp15 commands, handled by mrc/mcr.Øyvind Harboe2009-11-231-66/+0
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM11: remove unused state and exportsDavid Brownell2009-11-224-32/+25
| | | | | | | | | For now there's no point in saving this stuff after examine() checks it out as OK. Ditto exporting symbols that aren't used outside of the module which defines them. In fact, those two things needlessly complicate the code... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: macro cleanupDavid Brownell2009-11-222-72/+39
| | | | | | | | | | | | | | | | | Make this code look more like the rest of the OpenOCD code. - Use calloc() directly, not NEW() ... and fix some potential memory leaks while we're at it. - Remove FNC_INFO ... it's a NOP that just clutters things, and it's trivial for developers to add tracing as needed. - Replace FNC_INFO_NOTIMPLEMENTED with LOG_WARNING calls; ditto. And stop having those call sites wrongly succeed! - Waste less space with the CHECK_RETVAL() macro. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* mips: remove dynamic arrays - reduces stack usageØyvind Harboe2009-11-221-5/+15
| | | | | | Allocate working memory dynamically. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* mips: use const for code sequencesØyvind Harboe2009-11-222-13/+13
| | | | | | | | This will allow data to be allocated in read only memory instead of on the stack. Speeds things up and reduces stack usage. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm11: do not use dynamic arraysØyvind Harboe2009-11-221-3/+6
| | | | | | Allocate working memory dynamically, caught by checkstack.pl Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* arm926ejs: fix warningsØyvind Harboe2009-11-221-2/+2
| | | | | | | | buf_set_u32() operated on an uninitialized stack variable with non-byte boundaries, which led to warnings about reading uninitialized stack. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: use arm_reg_current()David Brownell2009-11-223-61/+74
| | | | | | | | | | Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove needless string format #ifdefferyDavid Brownell2009-11-223-21/+22
| | | | | | | | We don't need to use size_t in these places; so it's easy to be rid of the need for this #ifdef and its MS-derived portability problems. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target: make register flags "bool"David Brownell2009-11-221-2/+2
| | | | | | Mostly for clarity, but it also saves code and data space. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell2009-11-2212-56/+53
| | | | | | Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* flash: dynamically allocate working storageØyvind Harboe2009-11-221-16/+52
| | | | | | Allocate working memory rather than using stack. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target: reduce stack usageØyvind Harboe2009-11-221-6/+20
| | | | | | | 4096 byte buffer allocated dynamically. Better for embedded OS's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* zy1000: un-break uart command after command handler refactoringØyvind Harboe2009-11-221-15/+19
| | | | | | Switched it to jim command to insulate it from command refactoring. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded: reduce stack usageØyvind Harboe2009-11-221-4/+9
| | | | | | | Allocate working structures on stack to avoid issues with path lengths + reduce stack usage. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded: do not allocate large temporary structures on stackØyvind Harboe2009-11-221-6/+61
| | | | | | | With -O3 when inlining aggressively the total stack usage will be the sum of many fn's, which can easily get out of hand. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* embedded: save stackØyvind Harboe2009-11-221-9/+15
| | | | | | | and also do not recaluate the crc32_table upon every invocation. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* zy1000: fix breakage in command parsing code for power commandØyvind Harboe2009-11-221-1/+1
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* build: fix breakage in building bin2charØyvind Harboe2009-11-221-1/+1
| | | | | | | bin2char build relied on $(builddir) which is not defined for arm-elf X builds at least. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* ARM: arm_set_cpsr() handles T and J bitsDavid Brownell2009-11-227-79/+52
| | | | | | | | | | | | | | Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: define two register utilitiesDavid Brownell2009-11-228-48/+122
| | | | | | | | | | | | | | Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM: simplify CPSR handlingDavid Brownell2009-11-2211-87/+103
| | | | | | | | | | | | | | Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove disabled register hooksDavid Brownell2009-11-222-93/+3
| | | | | | | | Minor cleanup of ARM11 register handling: remove disabled register hooks. This should all be handled by shared code, and this stuff is just clutter. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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