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* target.cfg: TAP id for Hilscher netX 500David Brownell2009-11-201-9/+7
| | | | | | Based on email from "Martin Kaul <martin.kaul@leuze.de>". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* update 'flash bank' usage in scriptsZachary T Welch2009-11-1939-45/+90
| | | | | Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
* ARM: "armv4_5" command prefix becomes "arm"David Brownell2009-11-164-4/+4
| | | | | | | | | | Rename the "armv4_5" command prefix to straight "arm" so it makes more sense for newer cores. Add a simple compatibility script. Make sure all the commands give the same "not an ARM" diagnostic message (and fail properly) when called against non-ARM targets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: ETM + ETB supportDavid Brownell2009-11-134-4/+15
| | | | | | | | | | | Kick in ETM (and ETB) support for ARM11. Tested on OMAP 2420, so update that configuration. (That's an ARM1136ejs, ETB, OpenGL ES1.1, C55x DSP, etc.) Also update the other ARM11 ETM + ETB targets in the tree to set up these modules. (Not tested.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX2* + ETB targets: hook up ETM and ETBDavid Brownell2009-11-132-1/+10
| | | | | | | ARM9 cores with an ETB will have a matching ETM. Hook them both up by default. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: label ETBs correctlyDavid Brownell2009-11-135-28/+26
| | | | | | | | | | | | | | | | | | Various cores with an ETB have its TAP misnamed ... either as a boundary scan TAP or as the iMX "Secure JTAG Controller" (which is, among other things, a JRC that could be used to shorten scan chains). Use the correct name for these TAPs, which we can recognize since their IDs were assigned by ARM and these chips all document the presence of an ETB. The 0x2b900f0f is ETB11; the 0x1b900f0f is an older module, just called "ETB". Also shrink the ETB's IR configuration; the default IR-Capture value is fine, and the mask can specify that all four bits are safe to check (per ARM documentation). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: (re)move some bogus reset_config linesDavid Brownell2009-11-104-13/+0
| | | | | | | General rule, this is all board-specific and doesn't belong in target config files. Some of these were just cosmetic. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* stm32.cfg: remove reset_configThomas Kindler2009-11-101-3/+0
| | | | | | | | | | | | | | | Here's a patch for the double-reset problem on STM32. I've tested downloading and debugging with GDB and Eclipse, and everything seems to work fine. This effectively sets reset_config to none. trst_only would also be ok, but that's better left to a board configuration file since not all boards wire it up. The NVIC is used to trigger reset, which at least on this chip also pulses nSRST so the whole system does get rest -- exactly once. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* ARM11: remove old mrc/mcr commandsØyvind Harboe2009-11-102-5/+5
| | | | | | Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* telo.cfg: fix search pathsØyvind Harboe2009-11-101-4/+4
| | | | | | | Add the missing "target/" prefix for scripts in the target folder. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* target.cfg: remove "-work-area-virt 0"David Brownell2009-11-0835-35/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* remove "-ircapture 0x1 -irmask 0x1" from stm32.cfgFreddie Chopin2009-11-011-2/+5
| | | | | | | | Gets rid of the runtime warning "stm32.bs: nonstandard IR mask" [dbrownell@users.sourceforge.net: line lengths, note issue, section ref] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target.cfg: use $_TARGETNAME for flashFreddie Chopin2009-10-3113-13/+13
| | | | | | | | | This gets rid of runtime warnings from the use of numbers. STM32 and LPC2103 were tested. Other LPC updates are the same, and so are safe. The CFI updates match other tested changes now in the tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PXA255: force reset configDavid Brownell2009-10-261-0/+4
| | | | | These chips need both SRST and TRST when debugging, and SRST doesn't gate JTAG.
* omap3530: target reset/init improvementsDavid Brownell2009-10-261-15/+25
| | | | | | | | | | | | | | | | | Now I can issue "reset halt" and have everything act smoothly; the vector_catch hardware is obviously not kicking in, but the rest of the reset sequence acts sanely. - TAP "setup" event enables the DAP, not omap3_dbginit (resolving a chicken/egg bug I noted a while back) - Remove stuff from omap3_dbginit which should never be used in event handlers - Cope better with slow clocking during reset Also, stop hard-wiring the target name: use the input params in the standard way, and set up $_TARGETNAME as an output param. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* fix syntax of mww phys.Øyvind Harboe2009-10-251-11/+11
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* mww_phys retired. Replaced by generic mww phys in target.cØyvind Harboe2009-10-211-11/+11
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* Added the faux flash driver and target. Used for testing.Øyvind Harboe2009-10-201-0/+29
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* davinci: add watchdog reset methodDavid Brownell2009-10-191-1/+62
| | | | | | Lightly tested on dm365. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX target config script's ported from Freescale BSP.Øyvind Harboe2009-10-141-0/+30
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* omap2420.cfg updatesDavid Brownell2009-10-141-5/+6
| | | | | | Remove ircapture/mask attributes. Add "srst_nogate". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* arm11 seems to gate JTAG when srst is assertedØyvind Harboe2009-10-132-3/+2
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* Merge commit 'origin/master'Øyvind Harboe2009-10-121-7/+12
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| * Fix reset delays and tinker with ID'sWookey2009-10-101-7/+12
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* | Supply default reset_config statement to make target scripts useful ↵Øyvind Harboe2009-10-122-1/+4
|/ | | | standalone and provide sensible default
* make PXA255 targets enumerate sort-of-OKDavid Brownell2009-10-081-3/+32
| | | | | | | | | | | | | | | | | | | Startup now mostly works, except that the initial target state is "unknown" ... previously, it refused to even start. Getting that far required fixing the ircapture value (which can never have been correct!) and the default JTAG clock rate, then providing custom reset script. The "reset" command is still iffy. DCSR updates, and loading the debug handler, report numerous DR/IR capture failures. But once that's done, "poll" reports that the CPU is halted (which it shouldn't be, this was "reset run"!), due to the rather curious reason "target-not-halted". Summary: you still can't debug these parts, but it's closer. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* make OMAP5912 resets more reliableDavid Brownell2009-10-071-0/+2
| | | | | | | Without some extra delay after releasing SRST, we seemed to be trying to talk to the TAP before it was ready to respond. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* iMX25 target supportJohn Rigby2009-10-071-0/+41
| | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Dragonite target scriptdbrownell2009-10-061-0/+31
| | | | | | | From: Nicolas Pitre <nico@fluxnic.net> git-svn-id: svn://svn.berlios.de/openocd/trunk@2806 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Add a new JTAG "setup" event; use for better DaVinci ICEpick support.dbrownell2009-10-053-21/+28
| | | | | | | | | | | | | | | | | The model is that this fires after scanchain verification, when it's safe to call "jtag tapenable $TAPNAME". So it will fire as part of non-error paths of "init" and "reset" command processing. However it will *NOT* trigger during "jtag_reset" processing, which skips all scan chain verification, or after verification errors. ALSO: - switch DaVinci chips to use this new mechanism - log TAP activation/deactivation, since their IDCODEs aren't verified - unify "enum jtag_event" scripted event notifications - remove duplicative JTAG_TAP_EVENT_POST_RESET git-svn-id: svn://svn.berlios.de/openocd/trunk@2800 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Get rid of needless OMAP and Davinci target config optionsdbrownell2009-10-055-38/+13
| | | | | | | so they provide better examples and are easier to maintain. git-svn-id: svn://svn.berlios.de/openocd/trunk@2797 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Updated reset event handling in omap3530 cfgmlu2009-10-021-2/+7
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2796 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove annoying EOL whitespace (again, sigh).dbrownell2009-09-304-62/+62
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2781 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* strip gdb config optionsoharboe2009-09-301-5/+0
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2779 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com> reset now worksoharboe2009-09-302-50/+189
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2778 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Don't provide invalid OMAP5912 IR capture value/mask attributesdbrownell2009-09-271-3/+3
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2762 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Update DM355 target config to know about ICEpick.dbrownell2009-09-251-5/+18
| | | | | | | Still defaults to nonstandard EMU0/EMU1 settings. git-svn-id: svn://svn.berlios.de/openocd/trunk@2757 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Michael Hasselberg <mh@open-engineering.de> target configuration files for ↵oharboe2009-09-252-0/+112
| | | | | | Toshiba TX09 familiy git-svn-id: svn://svn.berlios.de/openocd/trunk@2756 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Remove annoying end-of-line whitespace from tcl/* filesdbrownell2009-09-2155-455/+455
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2743 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Ensure that DaVinci chips can't start with a too-fast JTAG clock.dbrownell2009-09-213-0/+18
| | | | | | | | | | It can be sped up later, once it's known the PLLs are active. Note that modern tools from TI all use adaptive clocking; and that if that's done with OpenOCD, "too fast" is also a non-issue. git-svn-id: svn://svn.berlios.de/openocd/trunk@2740 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Reduced sleep time after reset mlu2009-09-191-1/+2
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2732 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.cmlu2009-09-181-18/+3
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2728 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Rolf Meeser <rolfm_9dq@yahoo.de> adds flash support for NXP's LPC2900 family ↵oharboe2009-09-161-0/+65
| | | | | | (ARM968E). git-svn-id: svn://svn.berlios.de/openocd/trunk@2715 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* Magnus Lundin <lundin@mlu.mine.nu> Disable poll while core register ↵oharboe2009-09-131-0/+2
| | | | | | initialization git-svn-id: svn://svn.berlios.de/openocd/trunk@2703 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* David Brownell <david-b@pacbell.net> oharboe2009-09-122-1/+12
| | | | | | | | | | | | | | Update the board config for the DaVinci DM355 EVM so the reset-init event handler does the rest of the work it should do: - minor PLL setup bugfixes - initialize the DDR2 controller - probe both NAND banks - initialize UART0 - enable the icache git-svn-id: svn://svn.berlios.de/openocd/trunk@2699 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* tap post reset event added. Allows omap3530 to send 100 runtest idle ↵oharboe2009-09-111-0/+2
| | | | | | tickle's after a TAP_RESET. git-svn-id: svn://svn.berlios.de/openocd/trunk@2696 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* syntax error fixoharboe2009-09-111-0/+1
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2689 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* michal smulski <michal.smulski@ooma.com> telo target/board scriptsoharboe2009-09-104-30/+1342
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2683 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* use "armv4_5 core_state arm" instead of soft_reset_halt, fewer side effectsoharboe2009-09-043-4/+5
| | | | git-svn-id: svn://svn.berlios.de/openocd/trunk@2672 b42882b7-edfa-0310-969c-e2dbd0fdcd60
* set ARM mode using explicit command rather than soft_reset_halt which has ↵oharboe2009-09-041-1/+1
| | | | | | lots of side effects. git-svn-id: svn://svn.berlios.de/openocd/trunk@2669 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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