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* cfg: add pic32 virtual banksSpencer Oliver2010-05-261-0/+7
| | | | | | make use of the new virtual bank flash driver. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* There are no variants of arm7tdmi targetFreddie Chopin2010-05-247-7/+7
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* All LPC2xxx chips are little endian and that cannot be changed - update ↵Freddie Chopin2010-05-247-53/+8
| | | | | | config scripts Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* add correct CPUTAPID value for LPC2129Freddie Chopin2010-05-241-6/+2
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Update "flash bank" helper comments for LPC2xxx chipsFreddie Chopin2010-05-248-7/+8
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* LPC23xx and LPC24xx after reset run on internal 4MHz RC oscillator, so ↵Freddie Chopin2010-05-241-1/+1
| | | | | | "flash bank" parameter should be 4000 (not 12000) Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* at91sam9260: use RCLKØyvind Harboe2010-05-211-19/+12
| | | | | | | | | | | | | It might be possible to get this target going without RCLK, but it would require more careful analysis and usage of the reset events. Enable fast memory accesses. Tested on an at91sam9260 custom board w/external DRAM and flash. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: update stm32 performance stick configSpencer Oliver2010-05-211-1/+8
| | | | | | | | | - As this is a complete unit, including jtag we might as welli nclude the jtag cfg. - Add missing id for the str750 that is also in the jtag chain. - Reduce jtag startup speed to 500kHz. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* board: dm355evm.cfg SDTIMR0/1 minor naming fixJon Povey2010-05-211-1/+1
| | | | | | | Register name fix; ref. TI document sprueh7d Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* reset: fix reset halt bugGary Carlson2010-05-191-23/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was finally able to figure out the cause of this problem. There are two parts to the patch. The first patch modifies the configuration file I originally generated for the Atmel AT91SAM9G20 board and achieves the following: +++ Splits the reset-init handler into a reset-start handler for some of the initial configuration activities and keeps the remainder in the reset-init handler as was the case before. This was the real issue that was causing the timing problems I identified before. This solution was confirmed with an o-scope on actual target hardware. +++ Adds a new instruction in the reset-start handler to disable fast memory accesses in the reset-start handler. When the target jtag clock is started out at 2 kHz during system clock initialization, memory writes (i.e. register write to enable external reset pin -- basically to RSTC_MR) are naturally slow and cause GDB keep-alive issues (refer to PATCH 2/2 for additional fixes). +++ Modifies the configuration file to use srst_only reset action. The reset-start/reset-init handler split also now allows the correct behavior to be used in the configuration file (previously had to use both SRST and TRST even though only SRST is actually used and connected on the evaluation board). +++ Adds external NandFlash configuration support to take advantage of flash driver added earlier. Doesn't fix any bugs but adds functionality that was marked as TBD before and thrown in when I did other work on the configuration file. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* at91rm9200 : reset_config should go to the board config fileMarc Pignat2010-05-182-2/+3
| | | | | | Let other boards do other things with srst and trst. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* scripts: update flash bank namesSpencer Oliver2010-05-139-18/+18
| | | | | | As the flash bank name is now unique update the scripts to suit. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* zy1000.cfg: gdb connect will fail first time without gdb-attachØyvind Harboe2010-05-121-0/+5
| | | | | | | gdb-attach does a reset init to make sure that the CFI probe will succeed upon first gdb connect. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* cfg: add stm32eval board configsSpencer Oliver2010-05-074-1/+29
| | | | | | | | Increase working area for stm3210e_eval.cfg. Add new configs for the following boards: STM321000B-EVAL, STM32100C-EVAL, STM32100B-EVAL Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* zy1000: it has a CFI chip, no need for the ecosflash driverØyvind Harboe2010-04-301-1/+2
| | | | | | | The ecosflash driver is no longer used by any of the config scripts. It is more useful to get more testing of CFI. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* Add Voipac PXA270 module supportMarek Vasut2010-04-261-0/+12
| | | | | | This patch adds support for the Voipac PXA270 module. Including NOR flash. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* Add VPACLink interface definitionMarek Vasut2010-04-261-0/+10
| | | | | | | This patch adds definition file for the Voipac VPACLink JTAG adaptor. The adaptor is combined JTAG/UART device. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* telo: update configuration scripts to matched master branchmichal smulski2010-04-244-65/+4
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* TCL SCRIPTS: fix command nameAntonio Borneo2010-04-153-3/+3
| | | | | | | Some tcl script has underline between the words "flash bank" resulting in 'invalid command name "flash_bank"'. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* TCL scripts: update to current "flash bank" syntaxAntonio Borneo2010-03-2612-20/+24
| | | | | | | | | | | | | | While "flash bank" syntax has been changed long ago, several tcl script are still not fully update. Fix following cases related with "cfi" driver: - syntax error: the mandatory <name> parameter is missing - warning: the <target> parameter is a number, instead of the target name - the comment line above the command does not report actual syntax Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* PARPORT: add PARPORTADDR tcl variableSpencer Oliver2010-03-163-3/+21
| | | | | | | Add PARPORTADDR tcl variable making it easier to change parallel port address in scripts. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* PIC32: add Microchip Explorer16 cfgSpencer Oliver2010-03-163-8/+14
| | | | | | | - add Microchip Explorer16 cfg using PIC32MX360F512L PIM. - remove reset config from PIC32 target cfg. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* rename jtag_nsrst_assert_width as adapter_nsrst_assert_widthDavid Brownell2010-03-152-2/+2
| | | | | | | | | | | Globally rename "jtag_nsrst_assert_width" as "adapter_nsrst_assert_width", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename jtag_nsrst_delay as adapter_nsrst_delayDavid Brownell2010-03-1551-54/+54
| | | | | | | | | | | Globally rename "jtag_nsrst_delay" as "adapter_nsrst_delay", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* rename jtag_khz as adapter_khzDavid Brownell2010-03-1542-69/+69
| | | | | | | | | | | Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. (We may want to update it to include a nag message too.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32MX: update cfg scriptSpencer Oliver2010-03-151-10/+23
| | | | | | | | The default config script will now dynamically setup the BMX registers in the reset init script. This will also work if the user overrides the default working area. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Add support for Bus Pirate as a JTAG adapter.Michal Demin2010-03-111-0/+26
| | | | | | | | This includes a driver and matching config file. This support needs to be enabled through the initial "configure" (use "--enable-buspirate"). Signed-off-by: Michal Demin <michaldemin@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32: add flash algorithm supportSpencer Oliver2010-03-101-4/+12
| | | | | | | | | | | | | Add flash algorithm support for the PIC32MX. Still a few things todo but this dramatically decreases the programing time, eg. approx programming for 2.5k test file. - without fastload: 60secs - with fastload: 45secs - with fastload and algorithm: 2secs. Add new devices to supported list. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* doc: not all debug adapters are "dongles"David Brownell2010-03-051-2/+3
| | | | | | | | | | | | | | | | | Talk more about "debug adapters" instead of only "dongles". Not all adapters are discrete widgets; some are integrated onto boards. If we only talk about "dongles" we rule out many valid setups, and help confuse some users (who may be using Dongle-free environments). Also start bringing out the point that JTAG isn't the only transport protocol, even though OpenOCD historically presumes "all is JTAG". (Not all debug adapters are JTAG adapters, or JTAG-only adapters.) Plus a few minor fixes (spelling etc) in the vicinity of those changes, and updates about FT2232H clocking issues (they can go faster than the older chips, and can support adaptive clocking). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC1768 updates, IAR board supportDavid Brownell2010-03-022-25/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Add board/redbee-usb.cfgMariano Alvira2010-02-281-0/+8
| | | | | | | | | | | The Redbee USB is a small form-factor usb stick from Redwire, LLC (www.redwirellc.com/store), built around a Freescale MC13224V ARM7TDMI + 802.15.4 radio (plus antenna). It includes an FT2232H for debugging, with Channel B connected to the mc13224v's JTAG interface (unusual) and Channel A connected to UART1. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* add board/redbee-econotag.cfg and JTAG supportMariano Alvira2010-02-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The Redbee Econotag is an open hardware development kit from Redwire, LLC (www.redwirellc.com/store), for the Freescale MC13224V ARM7TDMI + 802.15.4 radio. It includes both an MC13224V and an FT2232H (for JTAG and UART support). It has flexible power supply options. Additional features are: - inverted-F pcb antenna - 36 GPIO brought out to 0.1" pin header (includes all peripheral pins) - Reset button - Two push buttons (on kbi1-5 and kbi0-4) - USB-A connector, powered from USB - up to 16V external input - pads for optional buck inductor - pads for optional 32.768kHz crystal - 2x LEDS on TX_ON and RX_ON [ dbrownell@users.sourceforge.net: shrink lines; texi ] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Add target/mc13224v.cfgMariano Alvira2010-02-271-0/+54
| | | | | | | | | | | | | | | | | The MC13224V is a FreeScale ARM7TDMI based IEEE802.15.4 platform for Zigbee and similar low-power wireless applications. Using PIP (Platform In Package) technology, it integrates: an RF balun and matching network; a buck converter (only an external inductor is necessary); 96KB of SRAM; and 128KB of non-volatile memory. It has an integrated bootloader and can boot from a variety of sources: external SPI or I2C non-volatile memory, an image loaded over UART1, or the internal non-volatile memory. The image loaded from one of these sources is executed directly from SRAM starting at location 0x00400000. Open source development code at http://mc1322x.devl.org Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* CSB337 board cleanup (quasi-regression)David Brownell2010-02-201-0/+2
| | | | | | | | Get rid of new nasty warning: NOTE! Severe performance degradation without fast memory access enabled... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* LPC1768.cfg -- partial fixes for bogus reset-init handlerDavid Brownell2010-02-151-4/+4
| | | | | | | | | Cortex-M targets don't support ARM instructions. Leave the NVIC.VTOR setup alone, but comment how the whole routine looks like one big bug... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* target library: configuration files for openocd tested with Atmel SAM-ICE V6 ↵Viktar Palstsiuk2010-02-112-0/+119
| | | | | | JTAG. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* str730.cfg: fix incorrect mem regionsSpencer Oliver2010-02-091-2/+2
| | | | | | - update str73x mem regions to correct values. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* scripts: Phytec/LPC2350 config scriptsEthan Eade2010-02-042-0/+124
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* AT91R40008/Ethernut 3 configurationHarald Kipp2010-02-022-32/+95
| | | | | | | | | | Moved board specific settings from target/at91r40008.cfg to a new file board/ethernut3.cfg. Set correct CPUTAPID. Reset delay increased, see MIC2775 data sheet. Increased work area size from 16k to 128k. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/str7x: Reset init unlocks the flashEdgar Grimberg2010-02-022-2/+17
| | | | | | | | | | | For STR7x flash, the device cannot be queried for the protect status. The solution is to remove the protection on reset init. The driver also initialises the sector protect field to unprotected. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* flash/str7x: After reset init the flash is unlockedEdgar Grimberg2010-02-021-1/+9
| | | | | | | | | | | | | | The default state of the STR7 flash after a reset init is unlocked. The information in the flash driver now reflects this. The information about the lock status cannot be read from the flash chip, so the user is informed that flash info might not contain accurate information. [dbrownell@users.sourceforge.net: line length shrinkage] Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* interface: Changed parport address to LPT1Edgar Grimberg2010-01-211-5/+3
| | | | | | Changed the parport address to LPT1, since it's the most obvious default value. Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com>
* board configs -- unique names for flash chipsDavid Brownell2010-01-202-8/+6
| | | | | | | | Don't give the same names to both flash chips on two OMAP boards. For OSK, enable DCC downloads (removing a warning). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* tcl/target/at91sam3u4e.cfg: changed case in dependent fileMichael Grzeschik2010-01-201-1/+1
| | | | | | | | openocd does not start with the target configfile due to the case in the dependent config file. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Added Openmoko USB JTAG interface config file.Vladimir Zapolskiy2010-01-111-0/+10
| | | | | | | | Added interface config file for JTAG/RS232 debug board originally integrated to Neo 1973 and Neo FreeRunner phones. Adapter was tested with i.MX31, S3C2410 and AT91SAM9260 processors. Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
* parport (mostly) doc fixesDavid Brownell2010-01-091-0/+2
| | | | | | | | | | | | | | | | | | | The "parport_port" commands generally don't *require* a port_number; they're of the "apply any parameter, then print result" variety. Update the User's Guide accordingly. Some of those commands are intended to be write-once: parport_port, and parport_cable. Say so. Use proper EBNF for the parport_write_on_exit parameter. Parport address 0xc8b8 is evidently mutant. Say so in the "parport.cfg" file, to avoid breaking anyone with that mutant config. But update the User's Guide to include a sane example for the LP2 port. Finally document the "presto_serial" command. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* PIC32: enable ram executionSpencer Oliver2010-01-051-1/+17
| | | | | | add reset-init script to allow ram execution from reset, this is required for ejtag fastdata access. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Added ST FlashLINK interface config file.Antonio Borneo2010-01-021-0/+10
| | | | | | | | The relevant cable config is already in OpenOCD, but not a config for the JTAG adapter. I have tested with FlashLINK on ARM926. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
* Fix parport_dcl5 config file.Antonio Borneo2009-12-301-1/+1
| | | | Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* Added Open-BLDC board config file.Piotr Esden-Tempski2009-12-291-0/+7
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