| Commit message (Collapse) | Author | Age | Files | Lines |
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Define a proc which PCBs can easily override.
Also demonstrates how to add multiple TAP exepcted-id's
using arguments.
Added 0x3f0f0f0f as expected TAP-id. Old LPC2148 silicon
I happened to have on my desk?
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Make consistent use of hex memory size for flashing.
Delete stm32f10x_128k_eval.cfg. It has no product reference
nor any settings in it.
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ST recently rewamped (screwed up) their web site and broke all links.
Also match the chip names with those on the web site product
descriptions.
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End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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LPC2xxx do not require reset_config srst_pulls_trst. This can cause various "strange" problems when flashing the chip, because "reset halt" actually allows the chip to run for some short period of time and execute some code.
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
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If no srst is configured then default to using sysresetreq to
reset the target.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Due to commit e40aee2954d2beabe1d8c530d9ff1e564fb01f48 we now honour the
targets 'reset_config' setting. Previously we ignored the srst setting
for luminary targets.
Luminary targets have never supported using srst to reset into debug mode
so remove the option from the target configs files.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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When this config was updated in commit e3773e3e3d1f1ee0dbb0b69e8babe8419784d1c1
the old jtag declaration was not removed.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Rename Atmel target scripts which had wrong name ("at91" missing for ARM7 AT91SAM7..., "at" missing for AVR ATmega...)
Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
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noeeprom version of the config file for older versions of Floss-JTAG.
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STMicroelectronics controller SMI is not SPEAr specific.
Rename it and change name to every symbol in the code.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Modified spearsmi driver to include support for STR75x
Added missing initialization in tcl file for STR750
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Initial support for ST SPEAr310 and for the evaluation
board EVALSPEAr310 Rev. 2.0.
Scripts are split in generic for SPEAr3xx family and
specific for SPEAr310. This should easily allow adding
new members of the family.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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This patch finally adds support for i.MX51 based Genesi USA EfikaMX smarttop
board.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.
i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acassis@gmail.com>.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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measure_clk indicates ca. 3-4MHz, so 1MHz should be safe.
Added self_test proc used to test that rclk worked.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Signed-off-by: Peter Stuge <peter@stuge.se>
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srst_pulls_trst may be true on some (broken) LPC1768 boards but is
not true in general for the LPC1768.
Signed-off-by: Peter Stuge <peter@stuge.se>
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Provide new helper proc that can set up either an SWD or JTAG DAP
based on the transport which is in use -- mostly for SWJ-DP.
Also update some SWJ-DP based chips/targets to use it. The goal
is making SWD-vs-JTAG transparent in most places. SWJ-DP based chips
really need this flexible configuration to cope with debug adapters
that support different transports, without needing new target configs
for each transport or adapter.
For JTAG-DP, callers will use "jtag newtap" directly, as today; only
one chip-level transport option exists.
For SW-DP (e.g. LPC1[13]xx or EFM32, they'll use "swd newdap" directly
(part of an upcoming SWD transport patch). Again, only one transport
option exists, so hard-wiring is appropriate there.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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In previous patch, I have introduced again the symbol
"ocd_mem2array", now replaced by "mem2array".
Fix the error.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Setting the OMAP3530 DBGEN bit must be done in physical memory, so
update omap3_dbginit callback to use the new 'mww phys' command syntax.
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TCL procedures mrw and mmw, originally in DaVinci target code,
are duplicated in other TCL scripts.
Moved in a common helper file, and added help/usage description.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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the new Marvell PXA270M processor has a new TAPID: 0x89265013.
Attached you will find a patch for target/pxa270.cfg that will handle this.
I have also attached a board/colibri.cfg file to support the Colibri
PXA270 module by Toradex.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This new cmd adds the ability to choose the Cortex-M3
reset method used.
It defaults to using SRST for reset if available otherwise
it falls back to using NVIC VECTRESET. This is known to work
on all cores.
Move any luminary specific reset handling to the stellaris cfg file.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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- Update all Luminary config's to use a common target/stellaris.cfg.
- Add Luminary ek-lm3s6965 config.
- Increase working area for boards with more ram.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
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Use rclk and 100ms delay on ntrst
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Ca. 93kBytes/s flashing speed @ 10MHz JTAG clock
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Using the bundled JTAG/SWD debug support in JTAG mode
is optional on *all* of the EK boards.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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These don't need to use the on-board debuggers in JTAG mode.
Off-board is OK, as would be SWD mode.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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nice board to play with.
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Tests should that it needs to be as low as 100kHz to be
stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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crank up JTAG speed as soon as clocks are set up.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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The ability to set up the OSCDIV divider was missing.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
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Clear the enable bits for all clocks that are not set explicitly.
This is done to increase robustness by removing pre-existing
state.
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
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