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* Added configuration file for STM3220G-EVAL board.Laurent Charpentier2011-06-081-0/+11
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* Added configuration file for stm32f2xxx.Laurent Charpentier2011-06-081-0/+56
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* uptech2410Bear2011-06-021-0/+65
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* Board definition for mini6410/tiny6410 (ARM1176)Damjan Marion2011-05-291-0/+112
| | | | | | | The following mini6410/tiny6410 functions are available: init_6410 - initialize clock, timer, DRAM init_6410_flash - initializes NAND flash support install_6410_uboot - copies u-boot image into RAM and runs it
* SMDK6410 is not target, move file to boardDamjan Marion2011-05-291-0/+0
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* flash support (only full erase/write) for 568013 and 568037Rodrigo L. Rosa2011-05-182-4/+4
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* partial support for 568013 and 568037, target integration.Rodrigo L. Rosa2011-05-182-0/+146
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* beagleboard: add support for various icepick versionsØyvind Harboe2011-05-051-5/+4
| | | | The beagleboard icepick jtag tap id's vary.
* at91rm9200-ek: add low default communication speedJonas Hoerberg2011-05-051-0/+2
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* Add support for the lpc2460 targetAlexandre Pereira da Silva2011-05-031-0/+21
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* Make the lpc2xxx generic driver support romless partsAlexandre Pereira da Silva2011-05-031-3/+5
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* u8500.cfg : ste u8500 supportMichel Jaouen2011-04-281-0/+326
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* Add preliminary support for Freescale iMX53Luca Ellero2011-04-131-0/+51
| | | | Signed-off-by: Luca Ellero <lroluk@gmail.com>
* Add the REV A tap id to the LPC3250 configurationAlexandre Pereira da Silva2011-04-131-1/+8
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* at91: add at91sam9263 chip register definitionJean-Christophe PLAGNIOL-VILLARD2011-04-093-4/+238
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add chip register definition and generic init supportJean-Christophe PLAGNIOL-VILLARD2011-04-099-0/+416
| | | | | | | | | | | | | | for - pio - pmc - rstc - wdt - sdramc - smc Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* add at91sam9263-ek supportJean-Christophe PLAGNIOL-VILLARD2011-04-091-0/+63
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* add at91sam9261-ek supportJean-Christophe PLAGNIOL-VILLARD2011-04-091-0/+63
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add at91sam9261 chip register definitionJean-Christophe PLAGNIOL-VILLARD2011-04-092-0/+136
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* pandaboard: use new -dbgbase option to workaround broken ROM tableØyvind Harboe2011-04-021-1/+14
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* omap4430: cortex a9 and a8 are now merged againØyvind Harboe2011-03-221-1/+1
| | | | Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* omap4430: add Blaze configAaron Carroll2011-03-131-0/+6
| | | | Signed-off-by: Aaron Carroll <aaronc@ok-labs.com>
* omap4430: force hardware breakpoints for GDBAaron Carroll2011-03-131-0/+3
| | | | | | | Soft breakpoints are currently broken if the MMU is enabled due to incorrect cache flushing. Until this is fixed, force the use of hardware breakpoints. Signed-off-by: Aaron Carroll <aaronc@ok-labs.com>
* at91: add at91sam9g45 supportJean-Christophe PLAGNIOL-VILLARD2011-03-031-0/+16
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add at91sam9g10 supportJean-Christophe PLAGNIOL-VILLARD2011-03-031-0/+16
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91sam9260: update sram informationJean-Christophe PLAGNIOL-VILLARD2011-03-031-1/+6
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add at91sam9263 supportJean-Christophe PLAGNIOL-VILLARD2011-03-031-0/+20
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: add at91sam9261 supportJean-Christophe PLAGNIOL-VILLARD2011-03-031-0/+14
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91sam9: factorise cpu supportJean-Christophe PLAGNIOL-VILLARD2011-03-036-127/+70
| | | | | | | | all at91sam9 are nearly the same except sram and soc name Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* add at91rm9200-ek board supportJean-Christophe PLAGNIOL-VILLARD2011-02-231-0/+112
| | | | | | | | | | | | | | | | | tested with jlink sam-ice v5 while loading barebox (gdb) load Loading section .text, size 0x2f190 lma 0x21f00000 Loading section .rodata, size 0x931c lma 0x21f2f190 Loading section .data, size 0x29e8 lma 0x21f384ac Loading section .barebox_cmd, size 0x78c lma 0x21f3ae94 Loading section .barebox_initcalls, size 0x80 lma 0x21f3b620 Start address 0x21f00000, load size 243360 Transfer rate: 26 KB/sec, 13520 bytes/write. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* stm32: add ID for medium density device Rev ZLuca Ellero2011-02-181-4/+5
| | | | | | | stm32-discovery evaluation board (STM32F100RBTB6): reading device id register (0xE0042000) returns 0x10010420 Signed-off-by: Luca Ellero <lroluk@gmail.com>
* omap4430: Add JRC TAPID for PandaBoard REV EA1 (PEAP platforms)Luca Ellero2011-02-081-2/+12
| | | | | | | PandaBoard REV EA1 (Panda Early Adopter Program) has a different ID. This patch add alternate REV EA1 TAP id to configuration file Signed-off-by: Luca Ellero <lroluk@gmail.com>
* omap4430: fix reset sequenceAaron Carroll2011-02-021-8/+3
| | | | | | | | | * Write to the PRM reset control register should have been 'phys'; * Setup empty reset-assert handlers for the M3's, since the board-level reset takes care of them; * Remove the dbginit cruft, because it gets called implicitly on reset. Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
* TCL configs for OMAP4430 and PandaboardAaron Carroll2011-01-312-0/+112
| | | | Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
* - add xds100v2 configuaration fileMathias K2011-01-271-0/+8
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* Add another level of procedures to LPC2xxx initialization - procedures for ↵Freddie Chopin2011-01-097-21/+105
| | | | | | specific targets (setup_lpc<number>) take core clock and adapter clock as parameters. This way "constant" parameters (flash size and type, CPUTAPID, etc.) do not need to be copied if one wishes to change the "variable" parameters - like the core clock or adapter clock - in a board config file or somewhere else. Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
* Add common LPC2xxx setup procedure, use in all LPC2xxx files.Freddie Chopin2011-01-078-238/+85
| | | | Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
* actux3.cfg: add function to setup for u-boot debuggingMichael Schwingen2011-01-021-0/+22
| | | | Signed-off-by: Michael Schwingen <michael@schwingen.org>
* stm32: add stm32 xl family flash supportSpencer Oliver2010-12-232-2/+12
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* lpc2148: redo to the new target configuration schemeØyvind Harboe2010-12-221-46/+41
| | | | | | | | | | | | Define a proc which PCBs can easily override. Also demonstrates how to add multiple TAP exepcted-id's using arguments. Added 0x3f0f0f0f as expected TAP-id. Old LPC2148 silicon I happened to have on my desk? Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
* tcl/interface/flashlink.cfg: Fix broken ST URLTormod Volden2010-12-201-1/+1
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* tcl/board: Clean up STM32 EVAL boards configurationsTormod Volden2010-12-205-15/+8
| | | | | | | Make consistent use of hex memory size for flashing. Delete stm32f10x_128k_eval.cfg. It has no product reference nor any settings in it.
* tcl/board: Fix ST URLs in stm32* eval board configuration filesTormod Volden2010-12-204-8/+8
| | | | | | ST recently rewamped (screwed up) their web site and broke all links. Also match the chip names with those on the web site product descriptions.
* update IXP42x target / XBA board configMichael Schwingen2010-12-193-96/+130
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* Add support for Hilscher netX controllersMichael Trensch2010-12-1814-9/+428
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* TCL: fix non TCL commentsAntonio Borneo2010-12-1828-732/+732
| | | | | | | | End of line comments fixed with ';' before '#'. Added few additional 'space' to keep indentation in multi-line comments. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
* stm32: add STM32E-EVAL external memory config scriptSpencer Oliver2010-12-101-0/+56
| | | | Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
* remove srst_pulls_trst from LPC2xxx target scriptsFreddie Chopin2010-12-096-12/+6
| | | | | | LPC2xxx do not require reset_config srst_pulls_trst. This can cause various "strange" problems when flashing the chip, because "reset halt" actually allows the chip to run for some short period of time and execute some code. Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
* lpc2478 target config: CCLK as (mandatory) parameterRolf Meeser2010-12-051-4/+7
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* Add board config for Embedded Artists LPC2478-32Rolf Meeser2010-12-041-0/+148
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