From 6839618062f07a12bd969da8dc54546f96938b67 Mon Sep 17 00:00:00 2001 From: Michael Trensch Date: Thu, 16 Dec 2010 15:33:16 +0100 Subject: Add support for Hilscher netX controllers --- contrib/openocd.udev | 3 ++ tcl/board/hilscher_nxdb500sys.cfg | 40 +++++++++++++++++ tcl/board/hilscher_nxeb500hmi.cfg | 40 +++++++++++++++++ tcl/board/hilscher_nxhx10.cfg | 82 ++++++++++++++++++++++++++++++++++ tcl/board/hilscher_nxhx50.cfg | 40 +++++++++++++++++ tcl/board/hilscher_nxhx500.cfg | 42 +++++++++++++++++ tcl/board/hilscher_nxsb100.cfg | 29 ++++++++++++ tcl/interface/hilscher_nxhx10_etm.cfg | 10 +++++ tcl/interface/hilscher_nxhx500_etm.cfg | 10 +++++ tcl/interface/hilscher_nxhx500_re.cfg | 10 +++++ tcl/interface/hilscher_nxhx50_etm.cfg | 10 +++++ tcl/interface/hilscher_nxhx50_re.cfg | 10 +++++ tcl/target/hilscher_netx10.cfg | 31 +++++++++++++ tcl/target/hilscher_netx50.cfg | 50 +++++++++++++++++++++ tcl/target/hilscher_netx500.cfg | 47 +++++++++++++++++++ tcl/target/netx500.cfg | 32 ------------- 16 files changed, 454 insertions(+), 32 deletions(-) create mode 100644 tcl/board/hilscher_nxdb500sys.cfg create mode 100644 tcl/board/hilscher_nxeb500hmi.cfg create mode 100644 tcl/board/hilscher_nxhx10.cfg create mode 100644 tcl/board/hilscher_nxhx50.cfg create mode 100644 tcl/board/hilscher_nxhx500.cfg create mode 100644 tcl/board/hilscher_nxsb100.cfg create mode 100644 tcl/interface/hilscher_nxhx10_etm.cfg create mode 100644 tcl/interface/hilscher_nxhx500_etm.cfg create mode 100644 tcl/interface/hilscher_nxhx500_re.cfg create mode 100644 tcl/interface/hilscher_nxhx50_etm.cfg create mode 100644 tcl/interface/hilscher_nxhx50_re.cfg create mode 100644 tcl/target/hilscher_netx10.cfg create mode 100644 tcl/target/hilscher_netx50.cfg create mode 100644 tcl/target/hilscher_netx500.cfg delete mode 100644 tcl/target/netx500.cfg diff --git a/contrib/openocd.udev b/contrib/openocd.udev index bcec6afd..34a819c3 100644 --- a/contrib/openocd.udev +++ b/contrib/openocd.udev @@ -64,5 +64,8 @@ ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="664", GROUP="plugdev" ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c140", MODE="664", GROUP="plugdev" ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="664", GROUP="plugdev" +# Hilscher NXHX Boards +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0028", MODE="664", GROUP="plugdev" + LABEL="openocd_rules_end" diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg new file mode 100644 index 00000000..48aff354 --- /dev/null +++ b/tcl/board/hilscher_nxdb500sys.cfg @@ -0,0 +1,40 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for paired K4S561632C (64MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C13261 + mww 0x00100140 0x030D0121 + + puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)" + mww 0x00100100 0x0201000E + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank +flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME + +init +reset init diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg new file mode 100644 index 00000000..9accd98d --- /dev/null +++ b/tcl/board/hilscher_nxeb500hmi.cfg @@ -0,0 +1,40 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads disable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC8M32 (32MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0111 + + puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)" + mww 0x00100100 0x0101000E + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg new file mode 100644 index 00000000..4a6b972a --- /dev/null +++ b/tcl/board/hilscher_nxhx10.cfg @@ -0,0 +1,82 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx10.cfg] + +# Usually it is not needed to set srst_pulls_trst +# but sometimes it does not work without it. If you encounter +# problems try to line below +# reset_config trst_and_srst srst_pulls_trst +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1 + +# Par. Flash can only be accessed if DIP switch on the board is set in proper +# position and init_sdrambus was called. Don't call these functions if the DIP +# switch is in invalid position, as some outputs may collide. This is why this +# function is not called automatically +proc flash_init { } { + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x101C0100 0x01010008 + + flash probe 0 +} + +proc mread32 {addr} { + set value(0) 0 + mem2array value 32 $addr 1 + return $value(0) +} + +proc init_clocks { } { + puts "Enabling all clocks " + set accesskey [mread32 0x101c0070] + mww 0x101c0070 [expr $accesskey] + + mww 0x101c0028 0x00007511 +} + +proc init_sdrambus { } { + puts "Initializing external SDRAM Bus 16 Bit " + set accesskey [mread32 0x101c0070] + mww 0x101c0070 [expr $accesskey] + mww 0x101c0C40 0x00000050 + + puts "Configuring SDRAM controller for K4S561632E (32MB) " + mww 0x101C0140 0 + sleep 100 + #mww 0x101C0144 0x00a13262 + mww 0x101C0144 0x00a13251 + mww 0x101C0148 0x00000033 + mww 0x101C0140 0x030d0121 +} + +$_TARGETNAME configure -event reset-init { + halt + wait_halt 1000 + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + init_clocks +# init_sdrambus + + puts "" + puts "-------------------------------------------------" + puts "Call 'init_clocks' to enable all clocks" + puts "Call 'init_sdrambus' to enable external SDRAM bus" + puts "-------------------------------------------------" +} + +##################### +# Flash configuration +##################### + +#flash bank +#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init \ No newline at end of file diff --git a/tcl/board/hilscher_nxhx50.cfg b/tcl/board/hilscher_nxhx50.cfg new file mode 100644 index 00000000..d129d12e --- /dev/null +++ b/tcl/board/hilscher_nxhx50.cfg @@ -0,0 +1,40 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx50.cfg] + +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x1C000140 0 + mww 0x1C000144 0x00A12151 + mww 0x1C000140 0x030D0001 + + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x1C000100 0x01010008 + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/tcl/board/hilscher_nxhx500.cfg b/tcl/board/hilscher_nxhx500.cfg new file mode 100644 index 00000000..3f2ff56e --- /dev/null +++ b/tcl/board/hilscher_nxhx500.cfg @@ -0,0 +1,42 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sleep 100 + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0001 + + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x00100100 0x01010008 + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg new file mode 100644 index 00000000..f52af448 --- /dev/null +++ b/tcl/board/hilscher_nxsb100.cfg @@ -0,0 +1,29 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0001 + +} + +init +reset init diff --git a/tcl/interface/hilscher_nxhx10_etm.cfg b/tcl/interface/hilscher_nxhx10_etm.cfg new file mode 100644 index 00000000..d71a1a3d --- /dev/null +++ b/tcl/interface/hilscher_nxhx10_etm.cfg @@ -0,0 +1,10 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#interface +interface ft2232 +ft2232_device_desc "NXHX 10-ETM" +ft2232_layout comstick +ft2232_vid_pid 0x0640 0x0028 +jtag_khz 6000 diff --git a/tcl/interface/hilscher_nxhx500_etm.cfg b/tcl/interface/hilscher_nxhx500_etm.cfg new file mode 100644 index 00000000..fffab49c --- /dev/null +++ b/tcl/interface/hilscher_nxhx500_etm.cfg @@ -0,0 +1,10 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#interface +interface ft2232 +ft2232_device_desc "NXHX 500-ETM" +ft2232_layout comstick +ft2232_vid_pid 0x0640 0x0028 +jtag_khz 6000 diff --git a/tcl/interface/hilscher_nxhx500_re.cfg b/tcl/interface/hilscher_nxhx500_re.cfg new file mode 100644 index 00000000..bcd54fc2 --- /dev/null +++ b/tcl/interface/hilscher_nxhx500_re.cfg @@ -0,0 +1,10 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#interface +interface ft2232 +ft2232_device_desc "NXHX 500-RE" +ft2232_layout comstick +ft2232_vid_pid 0x0640 0x0028 +jtag_khz 6000 diff --git a/tcl/interface/hilscher_nxhx50_etm.cfg b/tcl/interface/hilscher_nxhx50_etm.cfg new file mode 100644 index 00000000..251d0769 --- /dev/null +++ b/tcl/interface/hilscher_nxhx50_etm.cfg @@ -0,0 +1,10 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#interface +interface ft2232 +ft2232_device_desc "NXHX 50-ETM" +ft2232_layout comstick +ft2232_vid_pid 0x0640 0x0028 +jtag_khz 6000 diff --git a/tcl/interface/hilscher_nxhx50_re.cfg b/tcl/interface/hilscher_nxhx50_re.cfg new file mode 100644 index 00000000..6e428fb8 --- /dev/null +++ b/tcl/interface/hilscher_nxhx50_re.cfg @@ -0,0 +1,10 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#interface +interface ft2232 +ft2232_device_desc "NXHX50-RE" +ft2232_layout comstick +ft2232_vid_pid 0x0640 0x0028 +jtag_khz 6000 diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg new file mode 100644 index 00000000..14ff95da --- /dev/null +++ b/tcl/target/hilscher_netx10.cfg @@ -0,0 +1,31 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#Hilscher netX 10 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx10 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + diff --git a/tcl/target/hilscher_netx50.cfg b/tcl/target/hilscher_netx50.cfg new file mode 100644 index 00000000..1129544e --- /dev/null +++ b/tcl/target/hilscher_netx50.cfg @@ -0,0 +1,50 @@ +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#Hilscher netX 50 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx50 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + +# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from +# DMA controller at init. This function will setup a dummy DMA to free this ares +# and must be called before using SDRAM +proc sdram_fix { } { + + mww 0x1c005830 0x00000001 + + mww 0x1c005104 0xBFFFFFFC + mww 0x1c00510c 0x00480001 + mww 0x1c005110 0x00000001 + + sleep 100 + + mww 0x1c00510c 0 + mww 0x1c005110 0 + mww 0x1c005830 0x00000000 + + puts "SDRAM Fix executed!" +} diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg new file mode 100644 index 00000000..3b9e3d8e --- /dev/null +++ b/tcl/target/hilscher_netx500.cfg @@ -0,0 +1,47 @@ +#Hilscher netX 500 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx500 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +proc mread32 {addr} { + set value(0) 0 + mem2array value 32 $addr 1 + return $value(0) +} + +# This function must be called on netX100/500 right after halt +# If it is called later the needed register cannot be written anymore +proc sdram_fix { } { + + set accesskey [mread32 0x00100070] + mww 0x00100070 [expr $accesskey] + mww 0x0010002c 0x00000001 + + if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { + puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" + } else { + puts "SDRAM Fix succeeded!" + } +} diff --git a/tcl/target/netx500.cfg b/tcl/target/netx500.cfg deleted file mode 100644 index 04a267ba..00000000 --- a/tcl/target/netx500.cfg +++ /dev/null @@ -1,32 +0,0 @@ -#Hilscher netX 500 CPU - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME netx500 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x07926021 -} - -# FIXME most reset config belongs in board code -reset_config trst_and_srst -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -# jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# that TAP is associated with a target -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME - -- cgit v1.2.3