From fcf1301e5269fdf734946ccf03177511f2eda851 Mon Sep 17 00:00:00 2001
From: Øyvind Harboe <oyvind.harboe@zylin.com>
Date: Wed, 21 Oct 2009 20:19:47 +0200
Subject: mww_phys retired. Replaced by generic mww phys in target.c
---
doc/openocd.texi | 51 --------------------------------
tcl/board/atmel_at91sam9260-ek.cfg | 2 +-
tcl/board/mini2440.cfg | 60 +++++++++++++++++++-------------------
tcl/board/olimex_sam9_l9260.cfg | 2 +-
tcl/board/unknown_at91sam9260.cfg | 2 +-
tcl/target/davinci.cfg | 22 +++++++-------
6 files changed, 44 insertions(+), 95 deletions(-)
diff --git a/doc/openocd.texi b/doc/openocd.texi
index de73bec7..e04b83c8 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5431,23 +5431,6 @@ Display cp15 register @var{regnum};
else if a @var{value} is provided, that value is written to that register.
@end deffn
-@deffn Command {arm720t mdw_phys} addr [count]
-@deffnx Command {arm720t mdh_phys} addr [count]
-@deffnx Command {arm720t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm720t mww_phys} addr word
-@deffnx Command {arm720t mwh_phys} addr halfword
-@deffnx Command {arm720t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@subsection ARM9 specific commands
@cindex ARM9
@@ -5508,23 +5491,6 @@ Else if that value is written using the specified @var{address},
or using zero if no other address is not provided.
@end deffn
-@deffn Command {arm920t mdw_phys} addr [count]
-@deffnx Command {arm920t mdh_phys} addr [count]
-@deffnx Command {arm920t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm920t mww_phys} addr word
-@deffnx Command {arm920t mwh_phys} addr halfword
-@deffnx Command {arm920t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@deffn Command {arm920t read_cache} filename
Dump the content of ICache and DCache to a file named @file{filename}.
@end deffn
@@ -5556,23 +5522,6 @@ If a @var{value} is provided, that value is written to that register.
Else that register is read and displayed.
@end deffn
-@deffn Command {arm926ejs mdw_phys} addr [count]
-@deffnx Command {arm926ejs mdh_phys} addr [count]
-@deffnx Command {arm926ejs mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm926ejs mww_phys} addr word
-@deffnx Command {arm926ejs mwh_phys} addr halfword
-@deffnx Command {arm926ejs mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@subsection ARM966E specific commands
@cindex ARM966E
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index 099d93df..06a54e23 100644
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 5
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 277f61ff..29819501 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -177,10 +177,10 @@ proc init_2440 { } {
# usb clock are off 12mHz xtal
#-----------------------------------------------
- arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg
- arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
- arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
- arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
+ arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
+ arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
+ arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
+ arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
@@ -188,45 +188,45 @@ proc init_2440 { } {
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
- arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
- arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ?
- arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
- arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
- arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
- arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
- arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
- arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
+ arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
+ arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ?
+ arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
+ arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
+ arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
+ arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
+ arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
+ arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
- arm920t mww_phys 0x56000000 0x007FFFFF # GPACON
+ arm920t mww phys 0x56000000 0x007FFFFF # GPACON
- arm920t mww_phys 0x56000010 0x00295559 # GPBCON
- arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
- arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
+ arm920t mww phys 0x56000010 0x00295559 # GPBCON
+ arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
+ arm920t mww phys 0x56000014 0x000007C2 # GPBDAT
- arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
- arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP
- arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
+ arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON
+ arm920t mww phys 0x56000028 0x0000FFFF # GPCUP
+ arm920t mww phys 0x56000024 0x00000020 # GPCDAT
- arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
- arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
+ arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON
+ arm920t mww phys 0x56000038 0x0000FFFF # GPDUP
- arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
- arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
+ arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON
+ arm920t mww phys 0x56000048 0x0000FFFF # GPEUP
- arm920t mww_phys 0x56000050 0x00001555 # GPFCON
- arm920t mww_phys 0x56000058 0x0000007F # GPFUP
- arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
+ arm920t mww phys 0x56000050 0x00001555 # GPFCON
+ arm920t mww phys 0x56000058 0x0000007F # GPFUP
+ arm920t mww phys 0x56000054 0x00000000 # GPFDAT
- arm920t mww_phys 0x56000060 0x00150114 # GPGCON
- arm920t mww_phys 0x56000068 0x0000007F # GPGUP
+ arm920t mww phys 0x56000060 0x00150114 # GPGCON
+ arm920t mww phys 0x56000068 0x0000007F # GPGUP
- arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
- arm920t mww_phys 0x56000078 0x000003FF # GPGUP
+ arm920t mww phys 0x56000070 0x0015AAAA # GPHCON
+ arm920t mww phys 0x56000078 0x000003FF # GPGUP
}
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index b5cd10ec..935d7cd5 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
# be enabled... use physical address.
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index 017f793f..7286a967 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 3
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index e1eb48f5..c14c98ea 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
- arm926ejs mww_phys [expr $timer2_phys + 0x20] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x20] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b
+ arm926ejs mww phys [expr $timer2_phys + 0x24] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
- arm926ejs mww_phys [expr $timer2_phys + 0x10] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x14] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x18] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x10] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x14] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x18] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
# WDTCR: put into pre-active state, then active
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
}
--
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